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1. 发明专利

JP2009099613A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009099613A
公开(公告)日：2009-05-07
申请号：JP2007267047
申请日：2007-10-12
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , Univ Of Tokushima , トヨタ自動車株式会社 , 国立大学法人徳島大学 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , UEDA HIROYUKI , UESUGI TSUTOMU , KACHI TORU , ONO YASUO , GO KINPEI , HU CHENGYU
IPC分类号： H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form an ohmic electrode by repairing damage by etching.
SOLUTION: A method of manufacturing a semiconductor device comprises: a surface layer forming step of forming a heterogeneous surface layer on a surface of a p-type nitride semiconductor; an etching step of exposing the surface of the p-type nitride semiconductor by removing part of the surface layer; an annealing step of subjecting the p-type nitride semiconductor after the etching step to a heating process; and an electrode forming step of forming electrodes on the surface of the p-type nitride semiconductor after the annealing step. The annealing step is characterized by being executed in a nitrogen or oxygen atmosphere at 700-1,200°C.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过蚀刻修复损伤来形成欧姆电极。解决方案：制造半导体器件的方法包括：在p型氮化物半导体的表面上形成非均匀表面层的表面层形成步骤; 蚀刻步骤，通过去除表面层的一部分来暴露p型氮化物半导体的表面; 在蚀刻步骤之后对p型氮化物半导体进行加热处理的退火步骤; 以及在退火步骤之后在p型氮化物半导体的表面上形成电极的电极形成步骤。退火步骤的特征在于在氮气或氧气氛中在700-1200℃下进行。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009038070A Nitride semiconductor device and manufacturing method thereof 审中-公开
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：JP2009038070A
公开(公告)日：2009-02-19
申请号：JP2007198552
申请日：2007-07-31
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , Univ Of Tokushima , トヨタ自動車株式会社 , 国立大学法人徳島大学 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , UEDA HIROYUKI , UESUGI TSUTOMU , KACHI TORU , ONO YASUO , GO KINPEI , HU CHENGYU
IPC分类号： H01L21/28 , H01L33/32 , H01L33/40 , H01L33/44 , H01S5/042
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a nitride semiconductor device comprising a p-type nitride semiconductor layer, an insulating film covering the nitride semiconductor layer and formed with a through hole, and a metal film in contact with the nitride semiconductor layer exposed at the bottom face of the through hole, which method being able to actualize good ohmic characteristics.
SOLUTION: A silicon oxide film 4 is formed on the surface of a p-type gallium nitride layer 2. Then, part of the silicon oxide film 4 is etched, and a through hole 6 reaching the surface of the gallium nitride layer 2 is formed. Then, silicon 8 adhered to the surface of the gallium nitride layer 2 is removed. Then, a metal film in contact with the surface of the gallium nitride layer 2 is formed. Then, the gallium nitride layer 2, the silicon oxide film 4, and the metal film are heat-treated. The process for removing the silicon 8 and the process for forming the metal film are carried out under atmosphere containing no silicon.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种氮化物半导体器件的制造方法，该氮化物半导体器件包括p型氮化物半导体层，覆盖氮化物半导体层并形成有通孔的绝缘膜，以及与氮化物半导体层暴露在通孔的底面，该方法能够实现良好的欧姆特性。解决方案：在p型氮化镓层2的表面上形成氧化硅膜4.然后，蚀刻氧化硅膜4的一部分，并且到达氮化镓层表面的通孔6 形成2。然后，去除附着在氮化镓层2的表面上的硅8。然后，形成与氮化镓层2的表面接触的金属膜。然后，对氮化镓层2，氧化硅膜4和金属膜进行热处理。去除硅8的工艺和形成金属膜的工艺在不含硅的气氛下进行。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008277413A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008277413A
公开(公告)日：2008-11-13
申请号：JP2007117004
申请日：2007-04-26
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UEDA HIROYUKI , ISHIGURO OSAMU , UESUGI TSUTOMU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To break trade-off between an on-resistance and a gate threshold voltage.
SOLUTION: The semiconductor device 10 includes a semiconductor lower layer 22, a first impurity diffusion control film 24a, a third impurity diffusion control film 24c, a semiconductor upper layer 26, a drain region 31 provided to a part of the semiconductor upper layer 26 on the first impurity diffusion control film 24a, a source region 35 provid to a part of the semiconductor upper layer 26 on the third impurity diffusion control film 24c, and a gate electrode 34 opposed to the semiconductor upper layer 26 between the drain region 31 and the source region 35. A p-type impurity in the semiconductor upper layer 26 is thin on the first impurity diffusion control film 24a and the third impurity diffusion control film 24c, but thick on the second region 22b of the semiconductor lower layer 22.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：打破导通电阻和栅极阈值电压之间的折衷。解决方案：半导体器件10包括半导体下层22，第一杂质扩散控制膜24a，第三杂质扩散控制膜24c，半导体上层26，设置到半导体上层的一部分的漏区31 在第一杂质扩散控制膜24a上的层26，提供给第三杂质扩散控制膜24c上的半导体上层26的一部分的源极区域35和与漏极区域之间的半导体上层26相对的栅电极34 31和源极区35.半导体上层26中的p型杂质在第一杂质扩散控制膜24a和第三杂质扩散控制膜24c上较薄，但在半导体下层22的第二区22b上较厚版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008205315A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2008205315A
公开(公告)日：2008-09-04
申请号：JP2007041371
申请日：2007-02-21
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , SOEJIMA SHIGEMASA , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, consisting of a group-III nitride semiconductor which forms an n-type or a p-type region only in the bottom of a trench groove.
SOLUTION: A mask 2 is formed on the surface of an n-GaN layer, and a trench groove 3 is formed by using ICP etching (Fig. 1b). Then, ion implantation of Mg is executed, by subjecting the mask 2, as it is, to heat treatment, thereby forming a p-type region 4 on the side and bottom of the trench groove 3 (Fig. 1c). Next, only the p-type region 4b of the side portion of the trench groove 3 is selectively etched by using a TMAH (tetramethylammonium hydroxide) solution (Fig. 1d). According to these steps, the p-type region 4a can be formed at the bottom of the trench groove 3 self-aligned with respect to the trench groove 3.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供由仅在沟槽的底部形成n型或p型区域的III族氮化物半导体构成的半导体器件的制造方法。解决方案：在n-GaN层的表面上形成掩模2，并通过ICP蚀刻形成沟槽3（图1b）。然后，通过对掩模2进行热处理，从而在沟槽3（图1c）的侧面和底部形成p型区域4，进行Mg的离子注入。接下来，通过使用TMAH（四甲基氢氧化铵）溶液（图1d）仅选择性地蚀刻沟槽3的侧部的p型区域4b。根据这些步骤，p型区域4a可以形成在相对于沟槽3自对准的沟槽3的底部。（C）2008，JPO＆INPIT

5. 发明专利

JP2008205314A Method of etching group iii nitride semiconductor, and semiconductor device manufacturing method 审中-公开
标题翻译：蚀刻III族氮化物半导体的方法和半导体器件制造方法
公开(公告)号：JP2008205314A
公开(公告)日：2008-09-04
申请号：JP2007041370
申请日：2007-02-21
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , KANECHIKA MASAKAZU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/306 , H01L33/32
摘要： PROBLEM TO BE SOLVED: To provide a method of etching a group-III nitride semiconductor that will not have a damaged layer generated, and to provide a manufacturing method of semiconductor device. SOLUTION: A specimen consisting of a p-GaN layer 1, an n-GaN layer 2 and a mask 3 is formed (Fig. 1a). The main surface of the p-GaN layer 1 is a c-face. Then, the specimen placed on a pedestal made of sapphire is subjected to ICP etching using a Cl 2 gas, thereby forming a needle structure 4 (Fig. 1b). Then, the needle structure 4 is removed through wet etching by using a TMAH (tetramethylammonium hydroxide) solution (Fig. 1c). In this way, a damage layer is prevented from being formed on the surface 1a of the exposed p-GaN layer 1. According to these steps, a contact hole can be formed without having to form the damage layer at the bottom surface. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种蚀刻不产生损坏层的III族氮化物半导体的方法，并提供半导体器件的制造方法。
解决方案：形成由p-GaN层1，n-GaN层2和掩模3组成的样品（图1a）。 p-GaN层1的主表面是c面。然后，将放置在由蓝宝石制成的基座上的试样用Cl 2 气体进行ICP蚀刻，从而形成针结构4（图1b）。然后，通过使用TMAH（四甲基氢氧化铵）溶液（图1c）通过湿法蚀刻去除针结构4。以这种方式，防止在暴露的p-GaN层1的表面1a上形成损伤层。根据这些步骤，可以形成接触孔而不必在底面形成损伤层。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008177515A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008177515A
公开(公告)日：2008-07-31
申请号：JP2007103054
申请日：2007-04-10
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UEDA HIROYUKI , KANECHIKA MASAKAZU , SOEJIMA SHIGEMASA , ISHIGURO OSAMU , UESUGI TSUTOMU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/78 , H01L29/12 , H01L29/739 , H01L29/786
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of smoothly discharging holes generated during the operation of a semiconductor device utilizing a nitride semiconductor. SOLUTION: The semiconductor device 1 has a p-type gallium nitride region 16 of gallium nitride which has a high dislocation density region 18 and a low dislocation density region 19. In a plane view of a semiconductor device 2, a switching structure is formed in a range wherein the low dislocation density region 19 exists. The semiconductor device 2 is further provided with a body electrode 20 brought into contact with the p-type gallium nitride region 16. The body electrode 20 is brought into contact with the high dislocation density region 18. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够平滑地排出利用氮化物半导体的半导体器件的操作期间产生的空穴的技术。解决方案：半导体器件1具有具有高位错密度区域18和低位错密度区域19的氮化镓的p型氮化镓区域16.在半导体器件2的平面图中，开关结构形成在低位错密度区域19存在的范围内。半导体器件2还设置有与p型氮化镓区域16接触的体电极20.体电极20与高位错密度区域18接触。版权所有（C）2008 ，JPO＆INPIT

7. 发明专利

JP2010050280A Nitride semiconductor device 审中-公开
标题翻译：氮化物半导体器件
公开(公告)号：JP2010050280A
公开(公告)日：2010-03-04
申请号：JP2008213193
申请日：2008-08-21
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , UEDA HIROYUKI , KANECHIKA MASAKAZU , UESUGI TSUTOMU , KACHI TORU
IPC分类号： H01L21/338 , H01L29/778 , H01L29/786 , H01L29/80 , H01L29/812
CPC分类号： H01L29/2003 , H01L21/28264 , H01L29/41766 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/7787 , H01L29/7788
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor device 2 which has normally-off characteristics.
SOLUTION: The nitride semiconductor device 2 has a nitride semiconductor layer 10, made of undoped AlGaN, laminated on a surface of a nitride semiconductor lower layer 8 made of undoped GaN. The nitride semiconductor layer 10 has a larger band gap than the nitride semiconductor lower layer 8, and forms a heterojunction with the nitride semiconductor lower layer 8. A gate insulating film 16 is formed on a surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion formed of a nitride aluminum film 15 and a portion formed of an insulating substance 14 containing oxygen or silicon. A range W2 where the nitride aluminum film 15 is formed is included in a range W1 where a gate electrode 18 is formed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有常关特性的氮化物半导体器件2。解决方案：氮化物半导体器件2具有层叠在由未掺杂的GaN制成的氮化物半导体下层8的表面上的由未掺杂的AlGaN制成的氮化物半导体层10。氮化物半导体层10具有比氮化物半导体下层8更大的带隙，并且与氮化物半导体下层8形成异质结。在氮化物半导体层10的表面上形成栅极绝缘膜16。膜16包括由氮化物铝膜15形成的部分和由含有氧或硅的绝缘物质14形成的部分。其中形成氮化物铝膜15的范围W2包括在形成栅电极18的范围W1中。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010027639A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010027639A
公开(公告)日：2010-02-04
申请号：JP2008183496
申请日：2008-07-15
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , KANECHIKA MASAKAZU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/49 , H01L29/80 , H01L29/812 , H01L29/872
CPC分类号： H01L29/8122 , H01L29/0623 , H01L29/0657 , H01L29/1029 , H01L29/1037 , H01L29/1075 , H01L29/1079 , H01L29/42316 , H01L29/7828 , H01L29/7832 , H01L29/7838 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a technology which decreases the on resistance while ensuring high breakdown voltage in a semiconductor device having a gate electrode provided between a pair of main electrodes.
SOLUTION: The semiconductor device 100 is provided with a gate electrode 10 between a pair of main electrodes 2 and 22. The gate portion 10 has an insulated gate electrode portion 10a and a Schottky electrode portion 10b. The semiconductor device 100 has a contact region 18 for connection with the main electrodes 2, a channel semiconductor region 8 which adjoins the contact region 18, a p-type semiconductor region 20 adjacent to the backside of the channel semiconductor region 8, and a drift semiconductor region 12 which adjoins both the channel semiconductor region 8 and the p-type semiconductor region 20. The insulated gate electrode portion 10a faces the surface of the contact region 18 with a gate insulating film 4 interposed therebetween. The Schottky electrode portion 10b is in direct contact with the surface of the drift semiconductor region 12.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在具有设置在一对主电极之间的栅电极的半导体器件中确保高击穿电压的同时降低导通电阻的技术。解决方案：半导体器件100在一对主电极2和22之间设置有栅电极10.栅极部分10具有绝缘栅电极部分10a和肖特基电极部分10b。半导体器件100具有用于与主电极2连接的接触区域18，与接触区域18相邻的沟道半导体区域8，与沟道半导体区域8的背面相邻的p型半导体区域20，半导体区域12，其与沟道半导体区域8和p型半导体区域20相邻。绝缘栅电极部分10a在其间插入有栅极绝缘膜4，面对接触区域18的表面。肖特基电极部分10b与漂移半导体区域12的表面直接接触。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009302388A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009302388A
公开(公告)日：2009-12-24
申请号：JP2008156824
申请日：2008-06-16
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UEDA HIROYUKI , KANECHIKA MASAKAZU , UESUGI TSUTOMU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L21/338 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To minimize a current leaking from an element region in a semiconductor device having a hetero-junction.
SOLUTION: A semiconductor device 100 has a semiconductor multilayer portion 11 where nitride semiconductor layers 6 and 10 having different band gaps are laminated, and the semiconductor multilayer portion 11 has an element region 100a and an element isolation region 100b formed around the element region 100a. The element region 100a is isolated from other regions by the element isolation region 100b. A step of manufacturing the semiconductor device 100 includes a step of forming a pair of electrode groups 24 and 16 which are connected with a main electrode on the surface of the semiconductor multilayer portion 11 in the element region 100a, and a step of forming a sputter layer 12 on the surface of the semiconductor multilayer portion 11 in the element isolation region 100b by using a sputtering method.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使具有异质结的半导体器件中的元件区域的电流泄漏最小化。解决方案：半导体器件100具有层叠有不同带隙的氮化物半导体层6和10的半导体多层部分11，并且半导体多层部分11具有元件区域100a和形成在元件周围的元件隔离区域100b 区域100a。元件区域100a通过元件隔离区域100b与其它区域隔离。制造半导体器件100的步骤包括在元件区域100a中形成与半导体多层部分11的表面上的主电极连接的一对电极组24和16的步骤，以及形成溅射层12通过溅射法在元件隔离区域100b中的半导体多层部分11的表面上。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009212291A Semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009212291A
公开(公告)日：2009-09-17
申请号：JP2008053543
申请日：2008-03-04
申请人： Hokkaido Univ , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 国立大学法人北海道大学 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , SOEJIMA SHIGEMASA , UESUGI TSUTOMU , KACHI TORU , HASHIZUME TAMOTSU , SATO TAKETOMO
IPC分类号： H01L21/338 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, reducing a reduction in drain current incidental to operating temperature rise in the semiconductor device having heterojunction of a nitride semiconductor layer.
SOLUTION: An HEMT 100 includes a semiconductor substrate 5 on which an undoped GaN layer 2 and an n-type AlGaN layer 4 are laminated in this order, a source electrode 6 and a drain electrode 10 formed on a surface of the semiconductor substrate 5 and a gate electrode 8 formed between the source electrode 6 and the drain electrode 10. A group of a plurality of recessed parts 14, each defining a first side face 12a extending in a direction of linking the source electrode 6 with the drain electrode 10 and a second side face 12b extending orthogonal to the first side face, is formed in the surface of the semiconductor substrate 5. The gate electrode 8 covers the first and second side faces 12a, 12b. In the HEMT 100, mesa-type conduction channels are connected in parallel.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件及其制造方法，减少了在具有氮化物半导体层的异质结的半导体器件中附带的工作温度升高的漏极电流的减少。解决方案：HEMT 100包括其上依次层叠未掺杂的GaN层2和n型AlGaN层4的半导体衬底5，形成在半导体的表面上的源电极6和漏电极10 基板5和形成在源极电极6和漏电极10之间的栅电极8.一组多个凹部14，每个凹部14限定在将源电极6与漏电极连接的方向上延伸的第一侧面12a 在半导体衬底5的表面上形成有与第一侧面正交的第二侧面12b和第二侧面12b。栅电极8覆盖第一和第二侧面12a，12b。在HEMT 100中，台面型导通通道并联连接。版权所有（C）2009，JPO＆INPIT

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