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    • 4. 发明申请
    • DIGITAL PLL CIRCUIT AND COMMUNICATION DEVICE
    • 数字PLL电路和通信设备
    • US20110164675A1
    • 2011-07-07
    • US13049645
    • 2011-03-16
    • Fumiaki SENOUEKouji Okamoto
    • Fumiaki SENOUEKouji Okamoto
    • H04N7/12H03L7/085
    • H03L7/087H03L7/091H03L2207/50
    • In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.
    • 在通过将参考信号的频率乘以频率指令字(频率比)而获得的频率输出时钟信号的数字PLL电路中,RPA串行地添加包含分数分量的频率指令字。 RPA的输出被输入到微小的相位误差发生器。 相位误差发生器基于频率指令字的串行相加值的小数部分产生接近参考信号的实际振幅值的多个阈值,计算参考信号的振幅值和相位误差的相位误差 基于阈值对应于振幅值的参考信号,并计算参考信号和输出时钟之间的微小相位误差。
    • 5. 发明申请
    • REACTOR FOR ELECTRICAL DEVICES
    • 电器用反应器
    • US20100245016A1
    • 2010-09-30
    • US12732464
    • 2010-03-26
    • Mitsutoshi KamedaKazuo KatoTakashi AokiHiroyuki OkuhiraKouji Okamoto
    • Mitsutoshi KamedaKazuo KatoTakashi AokiHiroyuki OkuhiraKouji Okamoto
    • H01F17/04
    • H01F37/00H01F17/04H01F27/255H01F27/324H01F41/0246H01F2017/048
    • A reactor includes a tubular coil and a core. The coil generates magnetic flux when a current is supplied thereto. The core is made of magnetic powder-containing resin, and is arranged to cover the coil. An entire surface of the coil is covered with an insulation coating. The insulation coating has corner portions that cover corner portions of the coil. The corner portions of the coil are formed between two opposing end surfaces (axial end surfaces) of the coil and an inner circumference surface of the coil, and between the two axial end surfaces of the coil and an outer circumference surface of the coil, when viewed in a cross section that is perpendicular to the direction the coil is wound. Each corner portion includes a curved surface portion formed with a circularly curved surface portion having a curvature radius of 0.2 mm or more. A minimum thickness of the corner portion is 0.2 mm or more. The elastic modulus of the core is 5 to 25 GPa.
    • 反应器包括管状线圈和芯。 当向其提供电流时,线圈产生磁通量。 芯由含磁性粉末的树脂制成,并且被布置成覆盖线圈。 线圈的整个表面覆盖有绝缘涂层。 绝缘涂层具有覆盖线圈的角部的角部。 线圈的角部形成在线圈的两个相对的端面(轴向端面)和线圈的内周面之间,并且在线圈的两个轴向端面和线圈的外周面之间形成,当 在垂直于卷绕方向的横截面中观察。 每个角部包括形成有曲率半径为0.2mm以上的圆形曲面部的曲面部。 角部的最小厚度为0.2mm以上。 芯的弹性模量为5至25GPa。
    • 7. 发明授权
    • Filter adjustment circuit
    • 滤波器调节电路
    • US07477099B2
    • 2009-01-13
    • US11792081
    • 2005-09-02
    • Kouji OkamotoTakashi MorieShiro DoshoHirokuni Fujiyama
    • Kouji OkamotoTakashi MorieShiro DoshoHirokuni Fujiyama
    • H03B1/00
    • H03G5/16H03H11/1291H03H11/20
    • In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
    • 在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中,来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2,然后由转换电路3转换成 数字信号。 来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。 两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制 基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果,以简单的电路结构,高精度地调整Gm-C滤波器2的响应特性的变化。
    • 8. 发明授权
    • Adaptive auto equalizer
    • 自适应自动均衡器
    • US06084907A
    • 2000-07-04
    • US986324
    • 1997-12-05
    • Kouichi NaganoKouji OkamotoTakashi YamamotoMasao Hamada
    • Kouichi NaganoKouji OkamotoTakashi YamamotoMasao Hamada
    • H03H21/00H03H7/30H03H7/40
    • H03H21/0012
    • In an adaptive auto equalizer for automatically amending a signal distorted through propagation in a transmission line to the expected value, each multiplication unit includes a plurality of weight coefficient holding units for storing weight coefficients. The number of these weight coefficient holding units is the same as the clock number which is equal to a delay required for updating the weight coefficients. An adder calculates weight coefficients every clock. The storage location of the calculated weight coefficients is switched by a selector, and the weight coefficients calculated every clock are serially held in a corresponding one of the weight coefficient holding units. The other selectors serially select one of the plurality of weight coefficient holding units and the weight coefficients thus held are given to the multiplication units. Consequently, each of the weight coefficients held in the weight coefficient holding units is given to a corresponding one of the multiplication units in a time period corresponding to the clock number equal to the delay time required for updating the weight coefficients. Thus, even if there is a delay before the update of the weight coefficients, an output error does not diverge, which makes it possible to obtain an ideal output signal in a short time and in a stable manner.
    • 在自适应自动均衡器中,用于自动修改通过传输线中的传播失真的信号到期望值,每个乘法单元包括用于存储权重系数的多个权重系数保持单元。 这些权重系数保持单元的数量与等于更新权重系数所需的延迟的时钟数相同。 加法器每个时钟计算加权系数。 计算的权重系数的存储位置由选择器切换,并且每个时钟计算的权重系数被连续地保持在相应的一个权重系数保持单元中。 其他选择器串行地选择多个权重系数保持单元中的一个,并且将这样保持的权重系数赋予乘法单元。 因此,保持在权重系数保持单元中的每个权重系数在对应于等于更新权重系数所需的延迟时间的时钟数的时间段中被给予相应的一个乘法单元。 因此,即使在更新加权系数之前存在延迟,输出误差也不会发散,这使得可以在短时间内以稳定的方式获得理想的输出信号。
    • 10. 发明授权
    • Digital PLL circuit, semiconductor integrated circuit, and display apparatus
    • 数字PLL电路,半导体集成电路和显示装置
    • US08648632B2
    • 2014-02-11
    • US13313638
    • 2011-12-07
    • Hiroki MouriKouji OkamotoFumiaki Senoue
    • Hiroki MouriKouji OkamotoFumiaki Senoue
    • H03L7/06
    • H03D13/003H03L7/087H03L2207/50
    • In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
    • 在数字PLL电路中,相位比较电路对参考时钟和振荡时钟的转换次数进行计数,将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段,以及 将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较, 时钟在相位比较时间段。 平滑电路平滑相位误差值。 数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。