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1. 发明授权

US07551213B2 Method for detecting vertical transfer defects in image sensors 有权
标题翻译：检测图像传感器垂直传输缺陷的方法
公开(公告)号：US07551213B2
公开(公告)日：2009-06-23
申请号：US11127250
申请日：2005-05-12
申请人： Toshiyuki Nakashima , Toshiya Kogishi , Kenji Arakawa , Toshinobu Hatano , Jun Kajiwara
发明人： Toshiyuki Nakashima , Toshiya Kogishi , Kenji Arakawa , Toshinobu Hatano , Jun Kajiwara
IPC分类号： H04N9/64 , H04N3/14 , H04N5/335
CPC分类号： H04N5/3675 , H04N5/361 , H04N5/3728
摘要： A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.
摘要翻译：通过转印部实现的电荷转移停止预定时间长度，用于将图像传感器元件中存储的图像传感器元件中的电荷沿着一个方向传送到图像传感器元件的表面上。在电荷转移停止预定的时间长度之后，电荷从传送部分传送而不读取图像传感器元件的电荷。基于传送的电荷的信号电平来识别图像拾取传感器中产生缺陷的位置。在包括缺陷产生位置并且与一个方向并行的线上生成的图像拾取传感器的缺陷信号电平被校正。作为上述处理的结果，精确地校正了显示故障。

2. 发明申请

US20050253939A1 Image processing method 有权
标题翻译：图像处理方法
公开(公告)号：US20050253939A1
公开(公告)日：2005-11-17
申请号：US11127250
申请日：2005-05-12
申请人： Toshiyuki Nakashima , Toshiya Kogishi , Kenji Arakawa , Toshinobu Hatano , Jun Kajiwara
发明人： Toshiyuki Nakashima , Toshiya Kogishi , Kenji Arakawa , Toshinobu Hatano , Jun Kajiwara
IPC分类号： H01L27/148 , H04N5/335 , H04N5/341 , H04N5/361 , H04N5/367 , H04N5/369
CPC分类号： H04N5/3675 , H04N5/361 , H04N5/3728
摘要： A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.
摘要翻译：通过转印部实现的电荷转移停止预定时间长度，用于将图像传感器元件中存储的图像传感器元件中的电荷沿着一个方向传送到图像传感器元件的表面上。在电荷转移停止预定的时间长度之后，电荷从传送部分传送而不读取图像传感器元件的电荷。基于传送的电荷的信号电平来识别图像拾取传感器中产生缺陷的位置。在包括缺陷产生位置并且与一个方向并行的线上生成的图像拾取传感器的缺陷信号电平被校正。作为上述处理的结果，精确地校正了显示故障。

3. 发明申请

US20050253954A1 Focus adjusting device and focus adjusting method 审中-公开
标题翻译：聚焦调整装置和调焦方法
公开(公告)号：US20050253954A1
公开(公告)日：2005-11-17
申请号：US11127209
申请日：2005-05-12
申请人： Toshiyuki Nakashima , Toshiya Kogishi , Kenji Arakawa , Toshinobu Hatano , Jun Kajiwara
发明人： Toshiyuki Nakashima , Toshiya Kogishi , Kenji Arakawa , Toshinobu Hatano , Jun Kajiwara
IPC分类号： G03B7/30 , G02B7/28 , G02B7/36 , G03B13/36 , H04N5/232 , H04N101/00
CPC分类号： H04N5/23212
摘要： A focus adjusting method for focusing a focus of a digital camera comprises an image signal converting step in which an imaging light entering an optical lens mechanism is converted into an image signal, an extracting step in which a high-frequency component of the image signal is selectively extracted, a signal generating step in which a luminance signal and a color difference signal are generated from the high-frequency component of the image signal selectively extracted, and a focus adjusting step in which a focusing position of the optical lens mechanism is adjusted using a high-frequency component of the luminance signal. According to the foregoing constitution, a focus adjustment can be realized with a high accuracy and at a high speed.
摘要翻译：用于聚焦数字照相机的焦点的聚焦调整方法包括图像信号转换步骤，其中进入光学透镜机构的成像光被转换为图像信号;提取步骤，其中图像信号的高频分量为选择性地提取信号产生步骤，其中从选择性地提取的图像信号的高频分量产生亮度信号和色差信号;以及聚焦调整步骤，其中调整光学透镜机构的聚焦位置，使用亮度信号的高频分量。根据上述结构，能够以高精度和高速度实现焦点调整。

4. 发明申请

US20050253936A1 Image processing device and image processing method 审中-公开
标题翻译：图像处理装置及图像处理方法
公开(公告)号：US20050253936A1
公开(公告)日：2005-11-17
申请号：US11119938
申请日：2005-05-03
申请人： Toshiya Kogishi , Jun Kajiwara , Kenji Arakawa , Toshinobu Hatano , Toshiyuki Nakashima
发明人： Toshiya Kogishi , Jun Kajiwara , Kenji Arakawa , Toshinobu Hatano , Toshiyuki Nakashima
IPC分类号： G06T1/00 , H04N1/46 , H04N1/60 , H04N9/04 , H04N9/73
CPC分类号： H04N9/735
摘要： An image processing device according to the present invention comprises an image signal operation unit, a correction data operation unit and a correcting unit. The image signal operation unit adjusts a white balance of an image signal by controlling a gain of the image signal for each color constituting the image signal. The correction data operation unit creates correction data for correcting an output of the image signal operation unit. The correcting unit further corrects the output of the image signal operation unit based on the correction data created by the correction data operation unit. According to the present invention, the white balance can be appropriately adjusted without losing subtle shades and shadows of a photographic object even in the case of an image signal including a noise level of a dark current.
摘要翻译：根据本发明的图像处理装置包括图像信号操作单元，校正数据操作单元和校正单元。图像信号操作单元通过控制构成图像信号的每种颜色的图像信号的增益来调整图像信号的白平衡。校正数据操作单元产生用于校正图像信号操作单元的输出的校正数据。校正单元还基于由校正数据操作单元创建的校正数据校正图像信号操作单元的输出。根据本发明，即使在包括暗电流的噪声电平的图像信号的情况下，也可以适当地调整白平衡，而不会损失摄影对象的微妙阴影和阴影。

5. 发明授权

US07750957B2 Pixel arranging apparatus, solid-state image sensing apparatus, and camera 有权
标题翻译：像素排列装置，固体摄像装置和照相机
公开(公告)号：US07750957B2
公开(公告)日：2010-07-06
申请号：US10970724
申请日：2004-10-22
申请人： Yoshihisa Shimazu , Ryouichi Nagayoshi , Toshiya Fujii , Toshiyuki Nakashima , Toshinobu Hatano , Jun Kajiwara , Kenji Arakawa , Toshiya Kogishi
发明人： Yoshihisa Shimazu , Ryouichi Nagayoshi , Toshiya Fujii , Toshiyuki Nakashima , Toshinobu Hatano , Jun Kajiwara , Kenji Arakawa , Toshiya Kogishi
IPC分类号： H04N5/335 , H04N3/14 , H01L27/00 , H01L31/113
CPC分类号： H04N9/045 , H04N5/3456
摘要： A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.
摘要翻译：一种固态摄像装置，包括固体摄像装置和信号处理电路。固体摄像装置包括：垂直传送单元，由对应于光 - 电转换元件的列的传送列组成，可操作以沿垂直方向传送从光 - 电转换元件读出的信号电荷，电转换元件; 水平传送单元，其可操作以从垂直传送单元接收信号电荷并在水平方向上传送它们。信号处理电路将来自水平传送单元的信号电荷转换为像素数据，并将其重新排列成二维阵列。在重新布置中，信号处理电路每次传送一个像素数据，循环选择三行存储器中的行存储器，将一条像素数据写入所选择的行存储器中，或从一行像素数据中读取一行像素数据选择行内存。

6. 发明申请

US20050104982A1 Pixel arranging apparatus, solid-state image sensing apparatus,and camera 有权
标题翻译：像素排列装置，固体摄像装置和照相机
公开(公告)号：US20050104982A1
公开(公告)日：2005-05-19
申请号：US10970724
申请日：2004-10-22
申请人： Yoshihisa Shimazu , Ryouichi Nagayoshi , Toshiya Fujii , Toshiyuki Nakashima , Toshinobu Hatano , Jun Kajiwara , Kenji Arakawa , Toshiya Kogishi
发明人： Yoshihisa Shimazu , Ryouichi Nagayoshi , Toshiya Fujii , Toshiyuki Nakashima , Toshinobu Hatano , Jun Kajiwara , Kenji Arakawa , Toshiya Kogishi
IPC分类号： H01L27/148 , H04N3/15 , H04N5/21 , H04N9/04 , H04N5/335
CPC分类号： H04N9/045 , H04N5/3456
摘要： A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.
摘要翻译：一种固态摄像装置，包括固体摄像装置和信号处理电路。固体摄像装置包括：垂直传送单元，由对应于光 - 电转换元件的列的传送列组成，可操作以沿垂直方向传送从光 - 电转换元件读出的信号电荷，电转换元件; 水平传送单元，其可操作以从垂直传送单元接收信号电荷并在水平方向上传送它们。信号处理电路将来自水平传送单元的信号电荷转换为像素数据，并将其重新排列成二维阵列。在重新布置中，信号处理电路每次传送一个像素数据，循环地选择三行存储器中的行存储器，将一条像素数据写入所选择的行存储器中，或从一行像素数据中读取一行像素数据选择行内存。

7. 发明申请

US20080055201A1 Panel interface device, LSI for image processing, digital camera and digital equipment 审中-公开
标题翻译：面板接口设备，图像处理LSI，数码相机和数字设备
公开(公告)号：US20080055201A1
公开(公告)日：2008-03-06
申请号：US11896359
申请日：2007-08-31
申请人： Jun Kajiwara
发明人： Jun Kajiwara
IPC分类号： G09G3/28
CPC分类号： G06F3/14 , G09G3/2003 , G09G2340/0414 , G09G2340/0421
摘要： The panel interface control device, which eliminates the necessity of newly producing video data for panel display and flexibly responds to a change in the type of display panel, includes a data conversion circuit and an RGB filter circuit that are both programmable and scale up or down a digital video signal for display horizontally and vertically to conform to the screen size of the display panel. An interface section outputs the output of the RGB filter circuit to the display panel as video data.
摘要翻译：面板接口控制装置不需要新生产用于面板显示的视频数据，并且灵活地响应显示面板类型的变化，包括可编程和缩小或缩小的数据转换电路和RGB滤波器电路用于水平和垂直显示的数字视频信号以符合显示面板的屏幕尺寸。接口部分将RGB滤波器电路的输出作为视频数据输出到显示面板。

8. 发明授权

US06833626B2 Multichip module structure 失效
标题翻译：多芯片模块结构
公开(公告)号：US06833626B2
公开(公告)日：2004-12-21
申请号：US10189549
申请日：2002-07-08
申请人： Jun Kajiwara , Masayoshi Kinoshita , Shiro Sakiyama
发明人： Jun Kajiwara , Masayoshi Kinoshita , Shiro Sakiyama
IPC分类号： H01L2940
CPC分类号： H01L25/16 , G01R31/2853 , G01R31/318513 , H01L27/10897 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2924/00014 , H01L2924/01019 , H01L2924/3011 , H01L2224/05599
摘要： A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.
摘要翻译：大芯片包括从第一干线导线分支并延伸到相应导线的第一组支线，以便连接到相应的接合焊盘。第一组的每条分支线包括连接控制元件和电阻器。小芯片包括从第二干线分支的第二组支线，并延伸到相应的导线，以便连接到相应的接合焊盘。第二组的每条分支线包括连接控制元件和电阻器。通过在对第一和第二测试焊盘施加电压时测量电流值来确定接合焊盘之间是否正确地进行连接。

9. 发明授权

US06809953B2 Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof 有权
标题翻译：电位发生电路，电位产生装置及使用其的半导体装置及其驱动方法
公开(公告)号：US06809953B2
公开(公告)日：2004-10-26
申请号：US10440277
申请日：2003-05-16
申请人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
发明人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
IPC分类号： G11C1122
CPC分类号： H02M3/07 , H02M3/073
摘要： A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through fourth periods are repeated.
摘要翻译：电位发生电路包括电容器（4）; 与电容器（4）串联连接的铁电电容器（6）。输出端子（11）; 用于使输出端子（11）接地的电容器（10）; 用于将两个电容器（4,6）之间的连接节点（5）连接到输出端子（11）的开关（9）; 和用于将连接节点（5）连接到地面的开关（1）; 其中在第一时段期间，当开关（1）和（9）处于断开状态时，端子（3）被提供有正电位并且端子（7）接地; 其中在所述第一周期之后的第二时段期间，所述端子（3）接地，并且所述开关（9）处于接通状态; 其中在所述第二时段之后的第三时段期间，所述开关（9）处于断开状态，所述开关（1）处于接通状态，并且所述端子（7）被提供有正电位; 其中在所述第三周期之后的第四周期期间，所述终端（7）接地; 并且其中重复第一至第四周期。

10. 发明授权

US06646342B2 Semiconductor chip and multi-chip module 有权
公开(公告)号：US06646342B2
公开(公告)日：2003-11-11
申请号：US10097140
申请日：2002-03-14
申请人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： H01L2334
CPC分类号： H01L23/50 , H01L23/5382 , H01L23/5383 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.

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