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1. 发明申请

US20060212656A1 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US20060212656A1
公开(公告)日：2006-09-21
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

2. 发明授权

US07467261B2 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US07467261B2
公开(公告)日：2008-12-16
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

3. 发明申请

US20060212683A1 Information processing system, pipeline processor, and computer readable recording medium in which busy judgment program is stored 失效
标题翻译：信息处理系统，流水线处理器和存储有忙碌判断程序的计算机可读记录介质
公开(公告)号：US20060212683A1
公开(公告)日：2006-09-21
申请号：US11157809
申请日：2005-06-22
申请人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
发明人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
IPC分类号： G06F15/00
CPC分类号： G06F9/3824
摘要： In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.
摘要翻译：在本发明中，为了能够毫不费力地进行寄存器的繁忙判断，并且在不增加用于将请求存储到流水线寄存器最后一级提供的寄存器中的硬件资源数量的请求在流水线处理器中的流水线寄存器的中途保留一个第一计数器，用于对插入在流水线寄存器中的判断部分之间的寄存器中的有效请求数进行计数，以及判断请求是否为有效请求和请求队列的第一计数器提供用于基于第一计数器计数的有效请求的数量来判断请求队列是否处于忙状态的忙判断部分，并且由判断部分根据忙碌判断的忙碌状态判断结果进行判断部分。

4. 发明授权

US07490219B2 Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors 失效
标题翻译：计数器根据具有多个流水线处理器的系统中的判断计数有效请求
公开(公告)号：US07490219B2
公开(公告)日：2009-02-10
申请号：US11157809
申请日：2005-06-22
申请人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
发明人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3824
摘要： In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.
摘要翻译：在本发明中，为了能够毫不费力地进行寄存器的繁忙判断，并且在不增加用于将请求存储到流水线寄存器最后一级提供的寄存器中的硬件资源数量的请求在流水线处理器中的流水线寄存器的中途保留一个第一计数器，用于对插入在流水线寄存器中的判断部分之间的寄存器中的有效请求数进行计数，以及判断请求是否为有效请求和请求队列的第一计数器，以及提供用于基于第一计数器计数的有效请求的数量来判断请求队列是否处于忙状态的忙判断部分，并且由判断部分根据忙碌判断的忙碌状态判断结果进行判断部分。

5. 发明申请

US20060117140A1 Memory control device and memory control method 审中-公开
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US20060117140A1
公开(公告)日：2006-06-01
申请号：US11066760
申请日：2005-02-28
申请人： Takao Matsui , Seishi Okada , Daisuke Itoh , Makoto Hataida , Toshikazu Ueki
发明人： Takao Matsui , Seishi Okada , Daisuke Itoh , Makoto Hataida , Toshikazu Ueki
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： Address information of target data is stored in an ELA register at the start of a cache excluding process performed by BackEviction, and a request processing unit continuously re-executes a data acquiring process while an address of data requested to be acquired by a processor is present in the ELA register. The address information of the target data is stored in an EWB buffer at the start of autonomous move-out performed by a processor, and the cache excluding process performed by BackEviction is stopped when the address of data subjected to BackEviction is present in the EWB buffer.
摘要翻译：目标数据的地址信息在由BackEviction执行的高速缓存排除处理开始时存储在ELA寄存器中，并且请求处理单元连续重新执行数据获取处理，同时存在由处理器请求获取的数据的地址在ELA寄存器中。目标数据的地址信息在由处理器执行的自主移出开始时被存储在EWB缓冲器中，并且当经过BackEviction的数据的地址存在于EWB缓冲器中时，停止由BackEviction执行的高速缓存排除处理。

6. 发明申请

US20060031641A1 Method and apparatus for controlling memory system 有权
标题翻译：用于控制存储器系统的方法和装置
公开(公告)号：US20060031641A1
公开(公告)日：2006-02-09
申请号：US10999972
申请日：2004-12-01
申请人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
发明人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
摘要翻译：高速缓存状态维持单元存储存储在高速缓冲存储器的每个条目中的数据的地址信息，并将每个条目的状态保持为“强修改”，“弱修改”，“共享”和“无效”中的任何一个。数据获取过程选择单元在接收到数据读取请求时，基于地址信息和状态来选择至少一个数据获取过程。读取数据传送单元从获取的数据中选择最新数据，并将最新数据传送到发出数据读取请求的处理器。缓存状态更新单元在注册数据的地址信息时根据数据读取请求的类型来更新条目的状态。

7. 发明授权

US07783840B2 Method and apparatus for controlling memory system 有权
标题翻译：用于控制存储器系统的方法和装置
公开(公告)号：US07783840B2
公开(公告)日：2010-08-24
申请号：US10999972
申请日：2004-12-01
申请人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
发明人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
摘要翻译：高速缓存状态维持单元存储存储在高速缓冲存储器的每个条目中的数据的地址信息，并将每个条目的状态保持为“强修改”，“弱修改”，“共享”和“无效”中的任何一个。数据获取过程选择单元在接收到数据读取请求时，基于地址信息和状态来选择至少一个数据获取过程。读取数据传送单元从获取的数据中选择最新数据，并将最新数据传送到发出数据读取请求的处理器。缓存状态更新单元在注册数据的地址信息时根据数据读取请求的类型来更新条目的状态。

8. 发明申请

US20110072216A1 Memory control device and memory control method 审中-公开
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US20110072216A1
公开(公告)日：2011-03-24
申请号：US12926390
申请日：2010-11-15
申请人： Takao Matsui , Seishi Okada , Daisuke Itoh , Makoto Hataida , Toshikazu Ueki
发明人： Takao Matsui , Seishi Okada , Daisuke Itoh , Makoto Hataida , Toshikazu Ueki
IPC分类号： G06F12/08
CPC分类号： G06F12/0822
摘要： Address information of target data is stored in an ELA register at the start of a cache excluding process performed by BackEviction, and a request processing unit continuously re-executes a data acquiring process while an address of data requested to be acquired by a processor is present in the ELA register. The address information of the target data is stored in an EWB buffer at the start of autonomous move-out performed by a processor, and the cache excluding process performed by BackEviction is stopped when the address of data subjected to BackEviction is present in the EWB buffer.
摘要翻译：目标数据的地址信息在由BackEviction执行的高速缓存排除处理开始时存储在ELA寄存器中，并且请求处理单元连续重新执行数据获取处理，同时存在由处理器请求获取的数据的地址在ELA寄存器中。目标数据的地址信息在由处理器执行的自主移出开始时被存储在EWB缓冲器中，并且当经过BackEviction的数据的地址存在于EWB缓冲器中时，停止由BackEviction执行的高速缓存排除处理。

9. 发明授权

US08048527B2 Shaped expanded graphite article and method for producing the same 有权
标题翻译：成形膨胀石墨制品及其制造方法
公开(公告)号：US08048527B2
公开(公告)日：2011-11-01
申请号：US10526350
申请日：2003-09-03
申请人： Yoshiaki Hirose , Takao Matsui
发明人： Yoshiaki Hirose , Takao Matsui
IPC分类号： B32B9/00
CPC分类号： C04B41/009 , C01B32/20 , C04B35/536 , C04B35/62218 , C04B41/5092 , C04B41/85 , C04B2235/608 , C04B2235/77 , C04B2235/9684 , Y10T428/30 , C04B41/5058
摘要： A formed exfoliated graphite article which comprises an oxidation-resistant coating layer formed at least in the surface layer portion thereof, preferably wherein the oxidation-resistant coating layer contains a boron element and a phosphorus element, the content of a boron element in the oxidation-resistant coating layer is 1 mass % or more, the content of a phosphorus in the oxidation-resistant coating layer is 0.1 mass % or more, and the oxidation-resistant coating layer is formed in a thickness of 0.5 μm or more.
摘要翻译：一种形成的剥离石墨制品，其至少在其表层部分形成有抗氧化涂层，优选地，其中抗氧化涂层含有硼元素和磷元素，氧化 - 耐酸性涂层为1质量％以上，耐氧化性涂层中的磷含量为0.1质量％以上，耐氧化性涂层形成为0.5μm以上。

10. 发明授权

US07852594B2 Device and method for specifying control value for controlling clearance between head and disk, and magnetic disk drive device 有权
标题翻译：用于指定用于控制磁头和磁盘之间的间隙的控制值的装置和方法以及磁盘驱动装置
公开(公告)号：US07852594B2
公开(公告)日：2010-12-14
申请号：US12156092
申请日：2008-05-28
申请人： Yoshihiko Maeda , Takao Matsui , Nobuhiro Kuwamura , Kenichi Kuramoto , Akihiro Sera
发明人： Yoshihiko Maeda , Takao Matsui , Nobuhiro Kuwamura , Kenichi Kuramoto , Akihiro Sera
IPC分类号： G11B21/02
CPC分类号： G11B5/6064 , G11B5/607
摘要： Embodiments of the present invention help to detect contact between a head and a magnetic disk more accurately in specifying a heater power value for adjusting a clearance between a head element portion and the disk. According to one embodiment, a hard disk controller/multiprocessing unit (HDC/MPU) measures amplitudes of read signals in a user data field DATA. A hard disk drive (HDD) fills a gap between servo data with single data sector. The HDC/MPU measures the amplitudes of read signals in each data sector at different heater power values. It determines the heater power value at which contact occurs from the measured values.
摘要翻译：本发明的实施例有助于在确定用于调节头元件部分和盘之间的间隙的加热器功率值时更准确地检测磁头和磁盘之间的接触。根据一个实施例，硬盘控制器/多处理单元（HDC / MPU）测量用户数据字段DATA中的读取信号的幅度。硬盘驱动器（HDD）填充伺服数据与单个数据扇区之间的间隙。 HDC / MPU以不同的加热器功率值测量每个数据扇区中读取信号的幅度。它从测量值确定接触发生的加热器功率值。

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