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1. 发明授权

US06339549B1 Semiconductor storage apparatus having main bit line and sub bit line 有权
标题翻译：具有主位线和子位线的半导体存储装置
公开(公告)号：US06339549B1
公开(公告)日：2002-01-15
申请号：US09501624
申请日：2000-02-09
申请人： Toshikatsu Jinbo , Hiroyuki Takahashi , Kazuo Watanabe , Naoaki Sudo , Koji Naganawa , Hironori Nakamura
发明人： Toshikatsu Jinbo , Hiroyuki Takahashi , Kazuo Watanabe , Naoaki Sudo , Koji Naganawa , Hironori Nakamura
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C5/063 , G11C7/18
摘要： To provide a semiconductor storage apparatus capable of reducing a chip area, one main bit line is provided to a plurality of sub bit lines commonly connected with drains of memory cell transistors, the plurality of the bit lines are connected to ends on one side of switches at a first stage, control terminals of which are respectively inputted with column selecting signals and ends on other side of the switches are commonly connected and connected to the main bit line via a switch at a second stage, a control terminal of which is inputted with a column selecting signal, the sub bit lines are wired to a first wiring layer, the main bit line is wired to a second wiring layer and the second wiring layer is wired with power source lines, lines of voltage control signals in erasing or writing and high voltage power supply lines in regions among the main bit lines.
摘要翻译：为了提供能够减小芯片面积的半导体存储装置，将一个主位线提供给与存储单元晶体管的漏极共同连接的多个子位线，多个位线连接到开关的一侧的端部在第一阶段，其控制端分别输入列选择信号并在开关的另一侧结束在第二级经由开关共同连接并连接到主位线，其控制端被输入列选择信号，子位线被布线到第一布线层，主位线被布线到第二布线层，并且第二布线层与电源线布线，擦除或写入中的电压控制信号线，主位线之间的高压电源线。

2. 发明授权

US06198685B1 Word-line driving circuit and semiconductor memory device 有权
标题翻译：字线驱动电路和半导体存储器件
公开(公告)号：US06198685B1
公开(公告)日：2001-03-06
申请号：US09516742
申请日：2000-03-01
申请人： Naoaki Sudo , Hiroyuki Takahashi , Toshikatsu Jinbo , Kazuo Watanabe , Koji Naganawa , Hironori Nakamura
发明人： Naoaki Sudo , Hiroyuki Takahashi , Toshikatsu Jinbo , Kazuo Watanabe , Koji Naganawa , Hironori Nakamura
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： There is provided a word-line driving circuit has: two P-channel type transistors which are connected in a flip-flop configuration and one of which is connected between a first power supply and a word line; an N-channel transistor which is connected between a signal obtained by decoding a low-order address and a gate of the above-mentioned one P-channel type transistor and which has its gate connected with a signal obtained by decoding a high-order address; a first NN-channel type transistor which is connected between a word line and a second power supply and which has its gate connected with the signal obtained by decoding a low-order address; and a second NN-channel type transistor which is connected between a word line and the second power supply and which has its gate connected with the signal obtained by decoding a high-order address.
摘要翻译：提供了一种字线驱动电路，具有：以触发器结构连接的两个P沟道型晶体管，其中一个连接在第一电源和字线之间; 连接在通过解码低位地址获得的信号和上述一个P沟道型晶体管的栅极之间并且其栅极与通过解码高阶地址获得的信号相连接的N沟道晶体管 ; 第一NN沟道型晶体管，其连接在字线和第二电源之间，并且其栅极与通过解码低阶地址获得的信号相连; 以及第二NN沟道型晶体管，其连接在字线和第二电源之间，并且其栅极与通过解码高阶地址获得的信号相连。

3. 发明授权

US06456549B1 Sense amplifier circuit and semiconductor storage device 失效
公开(公告)号：US06456549B1
公开(公告)日：2002-09-24
申请号：US09938968
申请日：2001-08-24
申请人： Naoaki Sudo , Hiroyuki Takahashi
发明人： Naoaki Sudo , Hiroyuki Takahashi
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance C0N and transistor PM1 may include a parasitic capacitance C0P that is essentially equivalent to C0N. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

4. 发明授权

US06301180B1 Sense amplifier circuit and semiconductor storage device 有权
标题翻译：感应放大器电路和半导体存储器件
公开(公告)号：US06301180B1
公开(公告)日：2001-10-09
申请号：US09660869
申请日：2000-09-13
申请人： Naoaki Sudo , Hiroyuki Takahashi
发明人： Naoaki Sudo , Hiroyuki Takahashi
IPC分类号： G11C702
CPC分类号： G11C7/065
摘要： According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance C0N and transistor PM1 may include a parasitic capacitance C0P that is essentially equivalent to C0N. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.
摘要翻译：根据一个实施例，锁存型读出放大器可以减小可能由读出放大器锁存使能信号的电容耦合产生的信号输入处的噪声。锁存型读出放大器可以包括在第一输入SA1和第一锁存节点N1之间的第一传输门TG1和第二输入SA2与第二锁存节点N2之间的第二传输门TG2。第一传输门可以包括互补晶体管NM1和PM1。晶体管NM1可以在控制栅极处接收控制信号/ SE，而晶体管PM1可以在控制栅极处接收互补的控制信号SE。晶体管NM1可以包括寄生电容C0N，并且晶体管PM1可以包括基本上等于C0N的寄生电容C0P。在这种布置中，通过控制信号SE的电容耦合产生的第一输入端SA1的噪声可以通过互补控制信号/ SE的电容耦合产生的噪声来减小和/或抵消。

5. 发明授权

US06456548B2 Sense amplifier circuit and semiconductor storage device 失效
标题翻译：感应放大器电路和半导体存储器件
公开(公告)号：US06456548B2
公开(公告)日：2002-09-24
申请号：US09938773
申请日：2001-08-24
申请人： Naoaki Sudo , Hiroyuki Takahashi
发明人： Naoaki Sudo , Hiroyuki Takahashi
IPC分类号： G11C702
CPC分类号： G11C7/065
摘要： According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance CON and transistor PM1 may include a parasitic capacitance COP that is essentially equivalent to CON. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.
摘要翻译：根据一个实施例，锁存型读出放大器可以减小可能由读出放大器锁存使能信号的电容耦合产生的信号输入处的噪声。锁存型读出放大器可以包括在第一输入SA1和第一锁存节点N1之间的第一传输门TG1和第二输入SA2与第二锁存节点N2之间的第二传输门TG2。第一传输门可以包括互补晶体管NM1和PM1。晶体管NM1可以在控制栅极处接收控制信号/ SE，而晶体管PM1可以在控制栅极处接收互补的控制信号SE。晶体管NM1可以包括寄生电容CON，并且晶体管PM1可以包括基本上等同于CON的寄生电容COP。在这种布置中，通过控制信号SE的电容耦合产生的第一输入端SA1的噪声可以通过互补控制信号/ SE的电容耦合产生的噪声来减小和/或抵消。

6. 发明授权

US07880214B2 Nonvolatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US07880214B2
公开(公告)日：2011-02-01
申请号：US11431569
申请日：2006-05-11
申请人： Naoaki Sudo , Kohji Kanamori
发明人： Naoaki Sudo , Kohji Kanamori
IPC分类号： H01L29/76
CPC分类号： H01L29/7887 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor storage device in which one unit cell comprises a select gate 3 (3a-3i) provided in a first region on a substrate 1; a floating gate 6 provided in a second region adjacent to the first region; a diffused region 7b adjacent to the second region and provided in a third region on the surface of the substrate 1; and a control gate 11 provided on the floating gate 6. The select gate 3 is divided into three or more in an erase block 23 composed of all unit cells, from each of which electrons are extracted from the floating gate, at the same time when an erase operation is performed. Each of the select gates 3a-3i, created by the division, is formed in a comb-like shape in which, when viewed from the direction of a normal line to a plane, a plurality of comb teeth extend from a common line. The comb teeth of a select gate (for example, 3b) are arranged in gaps between the comb teeth of an adjacent select gate (for example, 3a, 3c) at a predetermined spacing.
摘要翻译：一种非易失性半导体存储装置，其中一个单位电池包括设置在基板1上的第一区域中的选择栅极3（3a-3i）设置在与第一区域相邻的第二区域中的浮动栅极6; 与第二区域相邻并设置在基板1的表面的第三区域中的扩散区域7b; 以及设置在浮置栅极6上的控制栅极11.选择栅极3在由所有单位单元构成的擦除块23中被划分为三个或更多个，其中每一个从浮置栅极中提取电子，同时当执行擦除操作。通过分割产生的选择门3a-3i中的每一个形成为梳状形状，其中从法线方向看平面时，多条梳齿从公共线延伸。选择门（例如3b）的梳齿以预定间隔布置在相邻选择栅极（例如，3a，3c）的梳齿之间的间隙中。

7. 发明申请

US20090190395A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090190395A1
公开(公告)日：2009-07-30
申请号：US12341632
申请日：2008-12-22
申请人： Naoaki Sudo
发明人： Naoaki Sudo
IPC分类号： G11C16/06 , G11C5/14 , G11C7/00
CPC分类号： G11C16/30 , G11C5/147 , G11C8/08 , G11C16/08
摘要： Provided is a nonvolatile semiconductor memory device which can enhance a stable control of a voltage applied to a memory cell and has excellent capability of controlling a drain voltage. The nonvolatile semiconductor memory device includes: a plurality of memory cells; a write buffer receiving data to be written to the plurality of memory cells; a count circuit searching data input to the write buffer and determining bit number of data to be simultaneously programmed to the plurality of memory cells; a write circuit supplying a write voltage to the plurality of memory cells according to the data; and a voltage regulator supplying a control voltage (Vpb) to the write circuit, wherein the voltage regulator includes a controller Counting write bit number and supplying the control voltage (Vpb) according to the counted write bit number.
摘要翻译：提供了一种非易失性半导体存储器件，其可以增强对存储单元施加的电压的稳定控制，并且具有优异的控制漏极电压的能力。非易失性半导体存储器件包括：多个存储单元; 写入缓冲器，接收要写入多个存储器单元的数据; 搜索输入到写缓冲器的数据的计数电路，并确定要同时编程到多个存储器单元的数据的位数; 写入电路，根据该数据向多个存储单元提供写入电压; 以及向写入电路提供控制电压（Vpb）的电压调节器，其中所述电压调节器包括控制器对写入位数进行计数，并根据所述计数的写入位数提供所述控制电压（Vpb）。

8. 发明申请

US20060261400A1 Nonvolatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US20060261400A1
公开(公告)日：2006-11-23
申请号：US11431569
申请日：2006-05-11
申请人： Naoaki Sudo , Kohji Kanamori
发明人： Naoaki Sudo , Kohji Kanamori
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor storage device in which one unit cell comprises a select gate 3 (3a-3i) provided in a first region on a substrate 1; a floating gate 6 provided in a second region adjacent to the first region; a diffused region 7b adjacent to the second region and provided in a third region on the surface of the substrate 1; and a control gate 11 provided on the floating gate 6. The select gate 3 is divided into three or more in an erase block 23 composed of all unit cells, from each of which electrons are extracted from the floating gate, at the same time when an erase operation is performed. Each of the select gates 3a-3i, created by the division, is formed in a comb-like shape in which, when viewed from the direction of a normal line to a plane, a plurality of comb teeth extend from a common line. The comb teeth of a select gate (for example, 3b) are arranged in gaps between the comb teeth of an adjacent select gate (for example, 3a, 3c) at a predetermined spacing.
摘要翻译：一种非易失性半导体存储装置，其中一个单位单元包括设置在基板1上的第一区域中的选择栅极3（3 a-3 i）设置在与第一区域相邻的第二区域中的浮动栅极6; 与第二区域相邻并设置在基板1的表面的第三区域中的扩散区域7b; 以及设置在浮置栅极6上的控制栅极11.选择栅极3在由所有单位单元构成的擦除块23中被划分为三个或更多个，其中每一个从浮置栅极中提取电子，同时当执行擦除操作。通过划分产生的选择门3a-3i中的每一个形成为梳状形状，其中从法线到平面的方向观察时，多个梳齿从公共线。选择门（例如，3b）的梳齿布置在相邻选择栅极的梳齿之间的间隙（例如，3a，3c）中，以预定间隔布置。

9. 发明授权

US06937515B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06937515B2
公开(公告)日：2005-08-30
申请号：US10652229
申请日：2003-08-29
申请人： Naoaki Sudo , Hiroshi Sugawara , Naoichi Kawaguchi
发明人： Naoaki Sudo , Hiroshi Sugawara , Naoichi Kawaguchi
IPC分类号： G11C16/02 , G11C7/06 , G11C7/10 , G11C16/06 , G11C16/26 , G11C16/28 , G11C16/04
CPC分类号： G11C7/106 , G11C7/062 , G11C7/1021 , G11C7/1051 , G11C16/26 , G11C16/28
摘要： A semiconductor memory device has a reduced number of sense amplifiers to suppress an increase in chip size and power consumption as integration is increased. A semiconductor memory device can be adapted to read out from a memory cell array in pages or bursts can include sense amplifiers (2) for reading out data for a page length or burst length in two parts, including a first half and second half, and a page buffer (3) for storing data for the page length or burst length read out from a memory cell array (1) by the sense amplifier (2).
摘要翻译：半导体存储器件具有减少数量的读出放大器，以抑制芯片尺寸和功耗的增加，因为集成度增加。半导体存储器件可以适于以页面或突发形式从存储单元阵列读出，可以包括读出放大器（2），用于读出包括上半部分和第二半部分在内的两个部分中的页面长度或突发长度的数据，以及用于存储由读出放大器（2）从存储单元阵列（1）读出的页长或突发长度的数据的页缓冲器（3）。

10. 发明授权

US5812018A Voltage booster circuit 失效
标题翻译：升压电路
公开(公告)号：US5812018A
公开(公告)日：1998-09-22
申请号：US782281
申请日：1997-01-13
申请人： Naoaki Sudo , Toshio Takeshima
发明人： Naoaki Sudo , Toshio Takeshima
IPC分类号： G11C17/00 , G11C16/06 , H02M3/07 , H03K19/0948 , G05F3/02
CPC分类号： H02M3/073
摘要： In order to provide a voltage booster circuit to be controlled for generating either of a positive high voltage and a negative high voltage for economizing chip size, a voltage booster circuit of the invention, having a charge transfer circuit wherein charges are transfered from a lowest node (N10) to a highest node (N15), comprises switching means (1 and 2) for selecting one of a positive high voltage output mode and a negative high voltage output mode. A positive high voltage (VPP) is output from the highest node (N15) by supplying a power supply voltage (VCC) to the lowest node (N10) in the positive high voltage output mode, and a negative high voltage (VBB) is output from the lowest node (N10) by grounding the highest node (N15) in the negative high voltage output mode.
摘要翻译：为了提供要控制的升压电路以产生正高电压和负高电压以节省芯片尺寸，本发明的升压电路具有电荷转移电路，其中电荷从最低节点（N10）到最高节点（N15），包括用于选择正高压输出模式和负高压输出模式之一的开关装置（1和2）。通过在正高压输出模式中向最低节点（N10）提供电源电压（VCC），从最高节点（N15）输出正高电压（VPP），并输出负高电压（VBB）通过在负高压输出模式下将最高节点（N15）接地，从最低节点（N10）开始。

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