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1. 发明授权

US06339549B1 Semiconductor storage apparatus having main bit line and sub bit line 有权
标题翻译：具有主位线和子位线的半导体存储装置
公开(公告)号：US06339549B1
公开(公告)日：2002-01-15
申请号：US09501624
申请日：2000-02-09
申请人： Toshikatsu Jinbo , Hiroyuki Takahashi , Kazuo Watanabe , Naoaki Sudo , Koji Naganawa , Hironori Nakamura
发明人： Toshikatsu Jinbo , Hiroyuki Takahashi , Kazuo Watanabe , Naoaki Sudo , Koji Naganawa , Hironori Nakamura
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C5/063 , G11C7/18
摘要： To provide a semiconductor storage apparatus capable of reducing a chip area, one main bit line is provided to a plurality of sub bit lines commonly connected with drains of memory cell transistors, the plurality of the bit lines are connected to ends on one side of switches at a first stage, control terminals of which are respectively inputted with column selecting signals and ends on other side of the switches are commonly connected and connected to the main bit line via a switch at a second stage, a control terminal of which is inputted with a column selecting signal, the sub bit lines are wired to a first wiring layer, the main bit line is wired to a second wiring layer and the second wiring layer is wired with power source lines, lines of voltage control signals in erasing or writing and high voltage power supply lines in regions among the main bit lines.
摘要翻译：为了提供能够减小芯片面积的半导体存储装置，将一个主位线提供给与存储单元晶体管的漏极共同连接的多个子位线，多个位线连接到开关的一侧的端部在第一阶段，其控制端分别输入列选择信号并在开关的另一侧结束在第二级经由开关共同连接并连接到主位线，其控制端被输入列选择信号，子位线被布线到第一布线层，主位线被布线到第二布线层，并且第二布线层与电源线布线，擦除或写入中的电压控制信号线，主位线之间的高压电源线。

2. 发明授权

US06198685B1 Word-line driving circuit and semiconductor memory device 有权
标题翻译：字线驱动电路和半导体存储器件
公开(公告)号：US06198685B1
公开(公告)日：2001-03-06
申请号：US09516742
申请日：2000-03-01
申请人： Naoaki Sudo , Hiroyuki Takahashi , Toshikatsu Jinbo , Kazuo Watanabe , Koji Naganawa , Hironori Nakamura
发明人： Naoaki Sudo , Hiroyuki Takahashi , Toshikatsu Jinbo , Kazuo Watanabe , Koji Naganawa , Hironori Nakamura
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： There is provided a word-line driving circuit has: two P-channel type transistors which are connected in a flip-flop configuration and one of which is connected between a first power supply and a word line; an N-channel transistor which is connected between a signal obtained by decoding a low-order address and a gate of the above-mentioned one P-channel type transistor and which has its gate connected with a signal obtained by decoding a high-order address; a first NN-channel type transistor which is connected between a word line and a second power supply and which has its gate connected with the signal obtained by decoding a low-order address; and a second NN-channel type transistor which is connected between a word line and the second power supply and which has its gate connected with the signal obtained by decoding a high-order address.
摘要翻译：提供了一种字线驱动电路，具有：以触发器结构连接的两个P沟道型晶体管，其中一个连接在第一电源和字线之间; 连接在通过解码低位地址获得的信号和上述一个P沟道型晶体管的栅极之间并且其栅极与通过解码高阶地址获得的信号相连接的N沟道晶体管 ; 第一NN沟道型晶体管，其连接在字线和第二电源之间，并且其栅极与通过解码低阶地址获得的信号相连; 以及第二NN沟道型晶体管，其连接在字线和第二电源之间，并且其栅极与通过解码高阶地址获得的信号相连。

3. 发明授权

US08237287B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08237287B2
公开(公告)日：2012-08-07
申请号：US12929968
申请日：2011-02-28
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/485 , H01L23/3121 , H01L23/525 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.
摘要翻译：半导体器件包括：形成电路的基板;在基板上形成有多个布线层的多层布线层和形成在布线层的最上层的预定位置的焊盘;提供新的焊盘在多层布线层上的适当位置，以及设置有耦合新衬垫和衬垫的再分配线的再分配层。在半导体器件中：多层布线层包括用于向电路发送电信号的信号线和设置在再分配线或新焊盘和电路之间的布线层中的接地线; 地线被形成为对应于假定要设置新垫的位置，以及假定形成再分配线的路径; 并且再分配线沿着地线的至少一部分形成。

4. 发明申请

US20090027993A1 Semiconductor memory device and data storage method 失效
标题翻译：半导体存储器件和数据存储方法
公开(公告)号：US20090027993A1
公开(公告)日：2009-01-29
申请号：US12216673
申请日：2008-07-09
申请人： Tatsuya Ishizaki , Hironori Nakamura , Takayuki Kurokawa , Kenichi Ushikoshi
发明人： Tatsuya Ishizaki , Hironori Nakamura , Takayuki Kurokawa , Kenichi Ushikoshi
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1006 , G11C8/12
摘要： According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.
摘要翻译：根据本发明的一个方面，提供了一种用于存储基于数据的坐标信息定义多维空间的数据的半导体存储器件，包括：具有以格子图案排列的存储单元的单元阵列，用于存储数据; 选择并驱动激活沿行方向布置的存储单元的多个字线中的任一个的字线选择器; 写放大器/读出放大器向/从布置在列方向上的存储单元写入/读取数据; 一个放大器选择器，输入/输出来自所选择的一个写入放大器/读出放大器的数据; 以及地址转换电路，其基于数据的坐标信息产生要提供给字线选择器的行地址，并且通过将数据的坐标信息转换为一维地生成要提供给放大器选择器的列地址，尺寸信息。

5. 发明授权

US06242962B1 Level shift circuit having plural level shift stage stepwise changing potential range without applying large potential difference to component transistors 有权
标题翻译：电平移位电路具有多个电平移位级逐步改变电位范围而不对元件晶体管施加大的电位差
公开(公告)号：US06242962B1
公开(公告)日：2001-06-05
申请号：US09153611
申请日：1998-09-15
申请人： Hironori Nakamura
发明人： Hironori Nakamura
IPC分类号： H03K17687
CPC分类号： H03K3/356113 , H03K17/102
摘要： A level shift circuit has plural level shift stages connected in series between an input node and an output node for producing an output signal, and a first level shift stage, an intermediate level shift stage and a final level shift stage produce a first intermediate signal changed between a positive power level and a first negative level from an input signal changed between the positive power level and the ground level, a second intermediate signal changed between the ground level and the first negative level from the first intermediate signal and an output signal changed between the ground level and a second negative level twice large in absolute value than the first negative level, thereby preventing the component field effect transistors from the large potential difference between the positive power level and the second negative level.
摘要翻译：电平移位电路具有串联连接在输入节点和用于产生输出信号的输出节点之间的多个电平移位级，并且第一电平移位级，中间电平移位级和最终级移位级产生改变的第一中间信号在正功率电平和第一负电平之间从在正功率电平和地电平之间改变的输入信号之间，第二中间信号在地电平和第一负电平之间从第一中间信号改变，并且输出信号在接地电平和绝对值比第一负电平两倍大的第二负电平，从而防止分量场效应晶体管从正功率电平和第二负电平之间的大电位差。

6. 发明授权

US09030713B2 Data processing apparatus and data processing method 有权
标题翻译：数据处理装置及数据处理方法
公开(公告)号：US09030713B2
公开(公告)日：2015-05-12
申请号：US13175162
申请日：2011-07-01
申请人： Hironori Nakamura
发明人： Hironori Nakamura
IPC分类号： G06T1/60 , H04N19/423 , H04N1/405
CPC分类号： G06T1/60 , H04N1/405 , H04N19/423
摘要： Provided is a data processing method that is capable of high-speed processing without using a large cache memory, while correlating 2-dimensional parameters with a plurality of data without damaging the arrangement rule. Therefore, when there is a continuing M-line parameter after a previously read M-line parameter in a 2-dimensional table that is stored in an external memory 406, the contents of the cache memory 404 are updated with this continuing M-line parameter as the new parameter. When there is no continuing M-line parameter after the previously read M-line parameter in the 2-dimensional table, the contents of the cache memory 404 are updated with the continuing M-line parameter after returning to the starting line of the 2-dimensional table as the new parameter. Such an update rule is maintained even when the band, which is the processing unit, is changed, or even in the progress of band processing.
摘要翻译：提供了一种数据处理方法，其能够在不使用大型高速缓冲存储器的情况下进行高速处理，同时在不损害布置规则的情况下将二维参数与多个数据相关联。因此，当在存储在外部存储器406中的二维表中预先读取的M行参数之后存在连续的M行参数时，高速缓冲存储器404的内容将被该连续M行参数更新作为新参数。当在二维表中先前读取的M行参数之后没有持续的M行参数时，高速缓冲存储器404的内容在返回到2-维表的起始行之后用连续M行参数更新，三维表作为新参数。即使处理单元的频带发生变化，或甚至在频带处理的进行中，也能够维持这样的更新规则。

7. 发明授权

US08164793B2 Image processing apparatus and method 有权
标题翻译：图像处理装置及方法
公开(公告)号：US08164793B2
公开(公告)日：2012-04-24
申请号：US12511773
申请日：2009-07-29
申请人： Shigeru Fujita , Hiroki Horikoshi , Yasunori Fujimoto , Shinichi Miyazaki , Akira Ichimura , Hironori Nakamura
发明人： Shigeru Fujita , Hiroki Horikoshi , Yasunori Fujimoto , Shinichi Miyazaki , Akira Ichimura , Hironori Nakamura
IPC分类号： G06K1/00 , H04N1/46 , B41J29/38 , B41J2/015
CPC分类号： G06K15/107
摘要： In a multipass printing that performs a plurality of printing scans over a unit area of a print medium by using a leading head and a follower head, the multivalued image data for the leading head is distributed according to the print volume information for up to the preceding printing scan. Then, the multivalued image data for the leading head is subjected to the grayscale level reduction operation to generate binary data. Based on the binary data, the print volume information is updated, after which the multivalued image data for the follower head is distributed according to the print volume information. This causes a plurality of printing scans or a plurality of print heads, that print the same unit area, to have a correlation among them, with the result that dots on a plurality of planes when overlapped have an excellent scattering characteristic.
摘要翻译：在通过使用前导头和跟随头在打印介质的单位区域上执行多次打印扫描的多页打印中，用于前导头的多值图像数据根据打印体积信息被分配到最前面打印扫描。然后，对前导头的多值图像数据进行灰度级降低操作，以生成二进制数据。基于二进制数据，更新打印体积信息，然后根据打印量信息分配随机头的多值图像数据。这导致打印相同单位区域的多个打印扫描或多个打印头在它们之间具有相关性，结果是当重叠时多个平面上的点具有优异的散射特性。

8. 发明授权

US4891399A Thermoplastic resin-based molding composition 失效
标题翻译：基于热塑性树脂的模塑组合物
公开(公告)号：US4891399A
公开(公告)日：1990-01-02
申请号：US110129
申请日：1987-10-19
申请人： Hideo Ohkawa , Masakuni Chikushi , Hironori Nakamura , Shinji Funayama , Takashi Hashimoto , Takahiro Hirai
发明人： Hideo Ohkawa , Masakuni Chikushi , Hironori Nakamura , Shinji Funayama , Takashi Hashimoto , Takahiro Hirai
IPC分类号： C08K3/22 , C08K9/04 , C08K9/06 , C08L101/00
CPC分类号： C08K9/06 , C08K3/22 , C08K9/04 , C08L101/00
摘要： The thermoplastic polymeric molding composition of the invention has good moldability in shaping by injection molding, extrusion molding and compression molding and capable of giving shaped articles having good machinability in mechanical working such as cutting, grinding and latching. The composition is compounded from 2 to 70 parts by weight of a thermoplastic polymer such as a polyamide resin and from 98 to 30 parts by weight of a metallic filler such as zinc powder and zinc oxide powder having a surface coated with a water repellent agent such as silane coupling agents, titanate coupling agents and silicone fluids in a specified amount. A part of the above mentioned particulate filler may optionally be replaced with a fibrous filler such as glass fibers and carbon fibers so that the shaped articles of the molding composition may be imparted with increased impact strength.
摘要翻译：本发明的热塑性聚合物成型组合物通过注射成型，挤出成型和压缩成型在成形时具有良好的成型性，并且能够赋予在机械加工如切割，研磨和闭锁中具有良好机械加工性的成型制品。该组合物由2-70重量份的热塑性聚合物如聚酰胺树脂和98-30重量份的金属填料如锌粉和氧化锌粉末组成，其表面涂有防水剂如作为硅烷偶联剂，钛酸酯偶联剂和指定量的硅氧烷流体。上述颗粒填料的一部分可以任选地被诸如玻璃纤维和碳纤维之类的纤维填料代替，使得模塑组合物的成形制品可赋予更高的冲击强度。

9. 发明授权

US08436469B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08436469B2
公开(公告)日：2013-05-07
申请号：US13490871
申请日：2012-06-07
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/485 , H01L23/3121 , H01L23/525 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.
摘要翻译：一种半导体器件，包括：衬底，形成在衬底上的多层布线层，并且包括信号线和在信号线上方延伸的接地线，其中一条接地线朝向预定层的方向延伸，另一条所述接地线从所述接地线中的一条向所述预定层中的另一方向延伸，所述多层布线层上的第一焊盘，形成在所述多层布线层上的再分布层，包括第二焊盘，再分布线耦合所述第一和第二焊盘以及覆盖所述再分配线的绝缘膜，所述再分配线沿着所述接地线之一延伸到所述接地线之上，并且不沿着所述另一个所述接地线延伸。绝缘膜包括在第一接地线之一的端部上方露出第二焊盘的孔。

10. 发明授权

US08405219B2 Semiconductor device 有权
公开(公告)号：US08405219B2
公开(公告)日：2013-03-26
申请号：US13490871
申请日：2012-06-07
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
摘要： A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.

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