专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070224546A1 Method of forming resist pattern and method of maufacturing semiconductor device 失效
标题翻译：形成抗蚀剂图案的方法和制造半导体器件的方法
公开(公告)号：US20070224546A1
公开(公告)日：2007-09-27
申请号：US11700131
申请日：2007-01-31
申请人： Toshifumi Suganaga , Tetsuro Hanawa , Takeo Ishibashi
发明人： Toshifumi Suganaga , Tetsuro Hanawa , Takeo Ishibashi
IPC分类号： G03F7/26
CPC分类号： G03F7/11 , G03F7/40
摘要： The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.
摘要翻译：本发明改进了由稀疏和密集掩模图案之间的差异产生的OPE特性，并提高了图案设计中的保真度。因此，本发明包括在基板上形成具有酸解离抑制基团的抗蚀剂的步骤，用溶解在醇系溶剂中的酸性聚合物涂布抗蚀剂并形成上层膜的工序，通过掩模曝光，进行烘烤处理的步骤和用碱性显影剂处理的步骤，并且其中在进行烘烤处理的步骤中，通过上层膜在抗蚀剂上形成混合层，并且在在图案密度低的区域中，掩模图案的图案密度高的区域的未曝光部分中形成较厚的混合层。

2. 发明授权

US07727709B2 Method of forming resist pattern and method of manufacturing semiconductor device 失效
标题翻译：形成抗蚀剂图案的方法和制造半导体器件的方法
公开(公告)号：US07727709B2
公开(公告)日：2010-06-01
申请号：US11700131
申请日：2007-01-31
申请人： Toshifumi Suganaga , Tetsuro Hanawa , Takeo Ishibashi
发明人： Toshifumi Suganaga , Tetsuro Hanawa , Takeo Ishibashi
IPC分类号： G03F7/26
CPC分类号： G03F7/11 , G03F7/40
摘要： The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.
摘要翻译：本发明改进了由稀疏和密集掩模图案之间的差异产生的OPE特性，并提高了图案设计中的保真度。因此，本发明包括在基板上形成具有酸解离抑制基团的抗蚀剂的步骤，用溶解在醇系溶剂中的酸性聚合物涂布抗蚀剂并形成上层膜的工序，通过掩模曝光，进行烘烤处理的步骤和用碱性显影剂处理的步骤，并且其中在进行烘烤处理的步骤中，通过上层膜在抗蚀剂上形成混合层，并且在在图案密度低的区域中，掩模图案的图案密度高的区域的未曝光部分中形成较厚的混合层。

3. 发明申请

US20100203456A1 METHOD OF FORMING RESIST PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成电阻图案的方法和制造半导体器件的方法
公开(公告)号：US20100203456A1
公开(公告)日：2010-08-12
申请号：US12767258
申请日：2010-04-26
申请人： Toshifumi Suganaga , Tetsuro Hanawa , Takeo Ishibashi
发明人： Toshifumi Suganaga , Tetsuro Hanawa , Takeo Ishibashi
IPC分类号： H01L21/027
CPC分类号： G03F7/11 , G03F7/40
摘要： The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.
摘要翻译：本发明改进了由稀疏和密集掩模图案之间的差异产生的OPE特性，并提高了图案设计中的保真度。因此，本发明包括在基板上形成具有酸解离抑制基团的抗蚀剂的步骤，用溶解在醇系溶剂中的酸性聚合物涂布抗蚀剂并形成上层膜的工序，通过掩模曝光，进行烘烤处理的步骤和用碱性显影剂处理的步骤，并且其中在进行烘烤处理的步骤中，通过上层膜在抗蚀剂上形成混合层，并且在在图案密度低的区域中，掩模图案的图案密度高的区域的未曝光部分中形成较厚的混合层。

4. 发明授权

US08017305B2 Pattern forming method, semiconductor device manufacturing method and exposure mask set 有权
标题翻译：图案形成方法，半导体器件制造方法和曝光掩模组
公开(公告)号：US08017305B2
公开(公告)日：2011-09-13
申请号：US12652470
申请日：2010-01-05
申请人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
发明人： Takeo Ishibashi , Takayuki Saito , Maya Itoh , Shuji Nakao
IPC分类号： G03F7/26
CPC分类号： G03F7/70466 , G03F1/00
摘要： First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
摘要翻译：首先，使用仅具有光栅图案形成区域的偶极照明作为要暴露的实质对象来执行第一曝光处理。接下来，仅以标准图案形成区域作为要曝光的实质物体进行第二曝光处理。然后进行显影处理以获得抗蚀剂图案。用于第一曝光处理的掩模使得在对应于标准图案形成区域的标准图案掩模部件的整个表面上形成遮光图案。用于第二曝光的掩模使得在对应于光栅图案形成区域的光栅图案掩模部分的整个表面上形成遮光图案。

5. 发明申请

US20090039519A1 SEMICONDUCTOR DEVICE, PHOTOMASK, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND PATTERN LAYOUT METHOD 审中-公开
标题翻译：半导体器件，光电子器件，半导体器件生产方法和图案布局方法
公开(公告)号：US20090039519A1
公开(公告)日：2009-02-12
申请号：US12187786
申请日：2008-08-07
申请人： Takayuki Saito , Takeo Ishibashi , Itaru Kanai
发明人： Takayuki Saito , Takeo Ishibashi , Itaru Kanai
IPC分类号： H01L23/48 , G03F1/00
CPC分类号： G03F1/36 , G03F1/00 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located on one side of the pad pattern in one of the plural columns, the pad pattern is connected to the line pattern located on the other side of the pad pattern in another column of the plural columns, and the line pattern located on one side of the pad pattern includes an open-circuit portion in another column. Therefore, a semiconductor device in which an interconnection pattern including the fine line-and-space-shape line pattern and the pad pattern is accurately formed at low cost, a semiconductor device production method, and a photomask used to produce the semiconductor device can be provided.
摘要翻译：根据本发明的一个方面的半导体器件包括多个线图案和多个衬垫图案。线图案重复地设置有插入其间的空间图案。焊盘图案跨越多列线图案。焊盘图案连接到位于多列之一中的焊盘图案的一侧的线图案，焊盘图案连接到位于多列的另一列中的焊盘图案另一侧的线图案，并且位于焊盘图案的一侧上的线图案包括另一列中的开路部分。因此，以低成本精确地形成包括细线和空间形线图案和焊盘图案的布线图形的半导体器件可以是用于制造半导体器件的半导体器件制造方法和光掩模提供。

6. 发明申请

US20060246380A1 Micropattern forming material and method for forming micropattern 审中-公开
标题翻译：微图案形成材料和形成微图案的方法
公开(公告)号：US20060246380A1
公开(公告)日：2006-11-02
申请号：US11354728
申请日：2006-02-15
申请人： Mamoru Terai , Toshiyuki Toyoshima , Takeo Ishibashi , Shinji Tarutani
发明人： Mamoru Terai , Toshiyuki Toyoshima , Takeo Ishibashi , Shinji Tarutani
IPC分类号： G03C5/00
CPC分类号： G03F7/40 , G03F7/2024 , H01L21/02118 , H01L21/02282 , H01L21/312
摘要： A micropattern forming material is formed on a resist pattern containing an acidic group. The micropattern forming material comprises a compound that penetrates the resist pattern. The penetration of the compound causes the resist pattern to form a crosslinked layer and thereby swell resulting in formation of a film insoluble in water or alkali.
摘要翻译：在含有酸性基团的抗蚀剂图案上形成微图案形成材料。微图案形成材料包括穿透抗蚀剂图案的化合物。化合物的渗透导致抗蚀剂图案形成交联层，从而溶胀，形成不溶于水或碱的膜。

7. 发明授权

US07030007B2 Via-filling material and process for fabricating semiconductor integrated circuit using the material 失效
标题翻译：通孔填充材料和使用该材料的半导体集成电路的制造工艺
公开(公告)号：US07030007B2
公开(公告)日：2006-04-18
申请号：US10623772
申请日：2003-07-22
申请人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
发明人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
IPC分类号： H01L21/47
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3127 , H01L21/76814
摘要： A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(═O)O— or —S(═O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
摘要翻译：通孔填充材料包括含有由氢，氟，氯，溴和甲基中的R 1〜1个表示的重复单元的聚合物; R 2是氢，C 1-3烷基和被取代氢的C 1-4烷基中的一个通过氟，氯和溴中的至少一种; 并且X是-C（-O）O-或-S（-O）2 O-。这种通孔填充材料在等离子体蚀刻期间不会在通孔的开口附近产生沉积物，并且提供具有高可靠性的半导体集成电路，即使当通过等离子体蚀刻形成通孔以外的沟槽时，通孔周围填充有通孔通孔填充材料。

8. 发明申请

US20050101123A1 Via-filling material and process for fabricating semiconductor integrated circuit using the material 失效
标题翻译：通孔填充材料和使用该材料制造半导体集成电路的工艺
公开(公告)号：US20050101123A1
公开(公告)日：2005-05-12
申请号：US10623772
申请日：2003-07-22
申请人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
发明人： Teruhiko Kumada , Toshiyuki Toyoshima , Hideharu Nobutoki , Takeo Ishibashi , Yoshiharu Ono , Junjiro Sakai
IPC分类号： C08L33/04 , C08F20/22 , C08L63/00 , H01L21/311 , H01L21/312 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/312 , H01L21/3127 , H01L21/76814
摘要： A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(═O)O or —S(═O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.
摘要翻译：通孔填充材料包括含有由氢，氟，氯，溴和甲基中的R 1〜1个表示的重复单元的聚合物; R 2是氢，C 1-3烷基和被取代氢的C 1-4烷基中的一个通过氟，氯和溴中的至少一种; 并且X是-C（-O）O或-S（-O）2 O-。这种通孔填充材料在等离子体蚀刻期间不会在通孔的开口附近产生沉积物，并且提供具有高可靠性的半导体集成电路，即使当通过等离子体蚀刻形成通孔以外的沟槽时，通孔周围填充有通孔通孔填充材料。

9. 发明申请

US20110221077A1 WATER REPELLANT COMPOSITION FOR SUBSTRATE TO BE EXPOSED, METHOD FOR FORMING RESIST PATTERN, ELECTRONIC DEVICE PRODUCED BY THE FORMATION METHOD, TREATMENT METHOD FOR IMPARTING WATER REPELLENCY TO SUBSTRATE TO BE EXPOSED, WATER REPELLANT SET FOR SUBSTRATE TO BE EXPOSED, AND TREATMENT METHOD FOR IMPARTING WATER REPELLENCY TO SUBSTRATE TO BE EXPOSED USING THE SAME 失效
标题翻译：用于形成耐蚀图案的水性组合物，形成方法生产的电子装置，用于将水再循环到底层以进行喷涂的处理方法，待被暴露的基材的水刷组合物，以及用于改变水的处理方法使用相同方式进行基材曝光
公开(公告)号：US20110221077A1
公开(公告)日：2011-09-15
申请号：US12867670
申请日：2009-02-20
申请人： Takeo Ishibashi , Miwako Ishibashi , Mamoru Terai , Takuya Hagiwara , Osamu Yokokoji , Yoko Takebe
发明人： Takeo Ishibashi , Miwako Ishibashi , Mamoru Terai , Takuya Hagiwara , Osamu Yokokoji , Yoko Takebe
IPC分类号： H01L23/00 , C09D5/00 , G03F7/20
CPC分类号： G03F7/16 , G03F7/11 , G03F7/2041
摘要： It is an object of the present invention to provide a water repellant composition for a substrate to be exposed which inhibits the back side of a substrate to be exposed from being contaminated by an immersion liquid, can improve adhesion between a film to be processed and an organic film directly overlying that film to inhibit film peeling, and has excellent workability, a method for forming a resist pattern, an electronic device produced by the formation method, a treatment method for imparting water repellency to a substrate to be exposed, a water repellent set for a substrate to be exposed, and a treatment method for imparting water repellency to a substrate to be exposed using the same. A water repellent composition for a substrate to be exposed including at least an organosilicon compound represented by the following general formula (1) and a solvent is used. In the formula, R1 is a monovalent organic group having 14 to 30 carbon atoms, each R2, R3, and R4 is independently a monovalent organic group or a hydrolyzable group having 1 to 10 carbon atoms, and at least one of R2, R3, and R4 is a hydrolyzable group.
摘要翻译：本发明的目的是提供一种抑制待暴露基板的背面被浸没液体污染的待曝光基材的防水组合物，可提高被处理膜与有机膜直接覆盖该膜以抑制膜剥离，并且具有优异的可加工性，形成抗蚀剂图案的方法，通过形成方法制造的电子器件，对待暴露的基底赋予拒水性的处理方法，防水剂设置为要暴露的基底，以及用于使用其进行曝光的基底赋予拒水性的处理方法。使用至少包含由以下通式（1）表示的有机硅化合物和溶剂的待曝光底物用防水组合物。式中，R1为碳原子数为14〜30的一价有机基团，R2，R3，R4分别独立为1价有机基团或碳原子数1〜10的可水解基团，R2，R3， R4是可水解基团。

10. 发明授权

US07935636B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07935636B2
公开(公告)日：2011-05-03
申请号：US12466549
申请日：2009-05-15
申请人： Takeo Ishibashi
发明人： Takeo Ishibashi
IPC分类号： H01L21/28 , H01L21/308
CPC分类号： G03F7/70341 , G03F9/7026 , G03F9/7065 , H01L21/28035 , H01L21/32139 , H01L29/6659 , Y10S438/95 , Y10S438/952
摘要： An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.
摘要翻译：绝缘膜形成在基板的主表面上。在绝缘膜上形成导电膜。在导电膜上形成下层抗蚀剂膜，中间层，抗反射膜和上层抗蚀剂膜。通过检测上层抗蚀剂膜的高度来检测曝光时的焦点。在检测曝光时的焦点时，焦点检测光被照射在上层抗蚀剂膜上。在检测到焦点之后，上层抗蚀剂膜被曝光和显影，从而形成抗蚀剂图案。以抗蚀剂图案作为掩模，对中间层和抗反射膜进行图案化，并且下层抗蚀剂膜显影。以这些图案作为掩模，对导电膜进行蚀刻从而形成栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式