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1. 发明专利

JP2013225584A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013225584A
公开(公告)日：2013-10-31
申请号：JP2012096879
申请日：2012-04-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/768 , H01L23/522 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being downsized.SOLUTION: A semiconductor device includes a semiconductor substrate in which active regions are sectioned on its upper layer portion, three lower vias provided directly above the active regions, and three upper vias having lower end portions each being in contact with upper end portions of the lower vias.
摘要翻译：要解决的问题：提供能够减小尺寸的半导体器件。解决方案：一种半导体器件包括半导体衬底，其中有源区在其上层部分上被分割，三个下部通孔直接设置在有源区上方，以及三个上部通孔具有各个下端部与下部通孔的上端部接触。

2. 发明专利

JP2013179193A Storage device and manufacturing method thereof 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：JP2013179193A
公开(公告)日：2013-09-09
申请号：JP2012042445
申请日：2012-02-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , KUTSUKAKE HIROYUKI , OUCHI KAZUYA , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L27/11543 , H01L29/401 , H01L29/788
摘要： PROBLEM TO BE SOLVED: To provide a storage device at low costs, and a manufacturing method thereof.SOLUTION: A storage device according to an embodiment comprises: a floating gate electrode film provided in a memory cell region; a first inter-electrode insulation film provided on the floating gate electrode film; a control gate electrode film provided on the first inter-electrode insulation film; a lower conductive film provided in a peripheral circuit region; a second inter-electrode insulation film provided on the lower conductive film; an upper conductive film provided on the second inter-electrode insulation film; and a pair of contacts isolated from each other, connected from the lower conductive film from above, and not connected to the upper conductive film. A material of the lower conductive film is same as a material of the floating gate electrode film. A material of the second inter-electrode insulation film is same as a material of the first inter-electrode insulation film. A material of the upper conductive film is same as a material of the control gate electrode film.
摘要翻译：要解决的问题：提供一种低成本的存储装置及其制造方法。根据实施例的存储装置包括：设置在存储单元区域中的浮栅电极膜; 设置在所述浮栅电极膜上的第一电极间绝缘膜; 设置在所述第一电极间绝缘膜上的控制栅极电极膜; 设置在外围电路区域中的下导电膜; 设置在下导电膜上的第二电极间绝缘膜; 设置在所述第二电极间绝缘膜上的上导电膜; 以及彼此隔离的一对触点，从上方与下导电膜连接，并且不连接到上导电膜。下导电膜的材料与浮栅电极膜的材料相同。第二电极间绝缘膜的材料与第一电极间绝缘膜的材料相同。上导电膜的材料与控制栅电极膜的材料相同。

3. 发明专利

JP2010251477A Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010251477A
公开(公告)日：2010-11-04
申请号：JP2009098302
申请日：2009-04-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , NOGUCHI MITSUHIRO , NAKAJIMA HIROOMI , ENDO MASATO
IPC分类号： H01L27/10
CPC分类号： H01L27/105 , H01L27/1021 , H01L27/1052 , H01L27/24
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that is advantageous to the increase of power consumption and a method of manufacturing the same.
SOLUTION: Each semiconductor memory device has a plurality of three-dimensionally structured memory cell arrays 10 that each have two or more memory cells and are multi-laminated on the semiconductor substrate 35, a first conductivity-type first well 43 prepared in a semiconductor substrate 35, and an element isolation insulating film STI having its bottom face at a position shallower than that of the first well 43 in the first well 43 and embedded and arranged in the semiconductor substrate 35. Further, it has a second well 44 having its bottom face at a position shallower than that of the first well 43 in the first well 43 (DP
摘要翻译：解决的问题：提供有利于增加功耗的半导体存储器件及其制造方法。解决方案：每个半导体存储器件具有多个三维结构的存储单元阵列10，每个存储单元阵列具有两个或更多个存储单元，并且多层叠在半导体衬底35上，第一导电型第一阱43 半导体衬底35和元件隔离绝缘膜STI，其底面位于比第一阱43中的第一阱43浅的位置，并嵌入并布置在半导体衬底35中。此外，它具有第二阱44 其底面位于比元件隔离绝缘膜STI的至少部分底面旁边准备的第一孔43（DP

4. 发明专利

JP2013026331A Manufacturing method of nonvolatile semiconductor memory device 审中-公开
标题翻译：非线性半导体存储器件的制造方法
公开(公告)号：JP2013026331A
公开(公告)日：2013-02-04
申请号：JP2011158012
申请日：2011-07-19
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11529 , H01L21/823425 , H01L21/823468 , H01L27/11524 , H01L29/6653
摘要： PROBLEM TO BE SOLVED: To prevent a sacrificial film such as a SiN film from remaining.SOLUTION: In the manufacturing method of a nonvolatile semiconductor memory device, a plurality of memory cell transistors and a plurality of selection transistors are formed on a substrate. Furthermore, first through fifth insulating films are buried sequentially between the memory cell transistors, between the memory cell transistor and the selection transistor, and between the selection transistors. Furthermore, the second and fourth insulating films between the selection transistors are removed by first etching so that parts of the second and fourth insulating films remain. Furthermore, the second and fourth insulating films remaining between the selection transistors are removed by second etching followed by the first etching.
摘要翻译：要解决的问题：为了防止SiN膜等牺牲膜残留。解决方案：在非易失性半导体存储器件的制造方法中，在衬底上形成多个存储单元晶体管和多个选择晶体管。此外，第一至第五绝缘膜依次埋设在存储单元晶体管之间，存储单元晶体管和选择晶体管之间以及选择晶体管之间。此外，通过第一蚀刻去除选择晶体管之间的第二和第四绝缘膜，使得第二和第四绝缘膜的一部分残留。此外，残留在选择晶体管之间的第二和第四绝缘膜通过第二次蚀刻然后进行第一次蚀刻而去除。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012160567A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2012160567A
公开(公告)日：2012-08-23
申请号：JP2011019058
申请日：2011-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , KUTSUKAKE HIROYUKI , NOGUCHI MITSUHIRO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11543 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of reducing the influence of a parasitic transistor formed in an end of an element region of a transistor.SOLUTION: A nonvolatile semiconductor memory device comprises: element regions 10A formed in a semiconductor substrate 10; first gate insulating films 14 formed on the element regions 10A; first gate electrodes 15 formed on the first gate insulating films 14; an inter-gate insulating film 16 that is formed on the first gate electrodes 15 and has openings; a second gate electrode 12 that is formed on the inter-gate insulating film 16 and contacts the first gate electrodes 15 through the openings; and element isolation regions 11 formed by the element regions 10A, the first gate insulating films 14, and the first gate electrodes 15 and surround the stacked structure. Cavities 18A are formed between the element isolation regions 11 and the side surfaces of the element regions 10A, the side surfaces of the first gate insulating films 14, and the side surfaces of the first gate electrodes 15.
摘要翻译：解决的问题：提供一种能够减小形成在晶体管的元件区域的端部的寄生晶体管的影响的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括：形成在半导体衬底10中的元件区10A; 形成在元件区域10A上的第一栅极绝缘膜14; 形成在第一栅极绝缘膜14上的第一栅电极15; 形成在第一栅电极15上并具有开口的栅极间绝缘膜16; 第二栅电极12，其形成在栅极间绝缘膜16上并通过开口与第一栅电极15接触; 以及由元件区域10A，第一栅极绝缘膜14和第一栅极电极15形成并且包围堆叠结构的元件隔离区域11。元件隔离区域11与元件区域10A的侧面，第一栅极绝缘膜14的侧面以及第一栅极电极15的侧面之间形成有空穴18A。（C） 2012年，JPO＆INPIT

6. 发明专利

JP2013179194A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013179194A
公开(公告)日：2013-09-09
申请号：JP2012042446
申请日：2012-02-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , KUTSUKAKE HIROYUKI
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/76 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with a high punch-through breakdown voltage, and a manufacturing method thereof.SOLUTION: A semiconductor device according to an embodiment comprises: a first conductive type semiconductor substrate; an element isolation insulator blocking an upper layer portion of the semiconductor substrate into plural active regions; a second conductive type source layer and a drain layer isolated from each other at an upper part of each active region; a gate electrode provided in a region immediately above a region between the source layer and the drain layer on the semiconductor substrate; a shield gate provided on the element isolation insulator; and a punch-through stopper layer that is of a first conductive type, the punch-through stopper layer having effective impurity concentration that is higher than an effective impurity concentration of the semiconductor substrate, one part contacting a lower face of the element isolation isolator, and being not formed in a region immediately above the gate electrode and a region immediately below the shield gate.
摘要翻译：要解决的问题：提供具有高穿孔击穿电压的半导体器件及其制造方法。根据实施例的半导体器件包括：第一导电类型半导体衬底; 元件隔离绝缘体，其将所述半导体衬底的上层部分阻挡成多个有源区; 在每个有源区的上部彼此隔离的第二导电型源极层和漏极层; 设置在半导体衬底上的源极层和漏极层之间的区域的正上方的区域中的栅极电极; 设置在元件隔离绝缘体上的屏蔽门; 以及穿透阻止层，其具有比半导体衬底的有效杂质浓度高的有效杂质浓度，一部分接触元件隔离隔离器的下表面的第一导电类型的穿通阻挡层，并且不形成在栅电极正上方的区域和屏蔽栅极正下方的区域。

7. 发明专利

JP2013062419A Semiconductor memory and method of manufacturing the same 审中-公开
标题翻译：半导体存储器及其制造方法
公开(公告)号：JP2013062419A
公开(公告)日：2013-04-04
申请号：JP2011200584
申请日：2011-09-14
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO TOKO , ENDO MASATO , NODA MITSUHIKO , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/76 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce degradation of element characteristics due to the stress of an element isolation insulating film.SOLUTION: A semiconductor memory includes a memory cell MC in a first active region AA including a charge storage layer on a first gate insulating film and a control gate electrode stacked on the charge storage layer, and a first transistor LT in a second active region AAL including a second gate insulating film 20L and a first electrode layer 21L on the second gate insulating film 20L. The second element isolation film 19X defining the second active region AAL includes a first film 190 and a second film 195 between the first film 190 and the second active region AAL, and the top surface of the first film 190 is located closer to the bottom side of a semiconductor substrate 10 than to the top surface of the second film 195.
摘要翻译：要解决的问题：为了减少元件隔离绝缘膜的应力引起的元件特性的劣化。解决方案：半导体存储器包括在第一有源区AA中的存储单元MC，其包括堆叠在电荷存储层上的第一栅绝缘膜上的电荷存储层和第二有源区中的第一晶体管LT 在第二栅极绝缘膜20L上包括第二栅极绝缘膜20L和第一电极层21L的有源区域AAL。限定第二有源区域AAL的第二元件隔离膜19X包括在第一膜190和第二有源区域AAL之间的第一膜190和第二膜195，并且第一膜190的顶表面位于更靠近底侧半导体衬底10相对于第二膜195的顶表面。版权所有：（C）2013，JPO＆INPIT

8. 发明专利

JP2011187625A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011187625A
公开(公告)日：2011-09-22
申请号：JP2010050479
申请日：2010-03-08
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , NOGUCHI MITSUHIRO , FUJII KENICHI , ARAI FUMITAKA
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768 , H01L21/8247 , H01L23/52 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/768 , H01L23/532 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device enabling downsizing regarding the semiconductor device particularly connecting two contacts vertically. SOLUTION: The semiconductor device includes: a first contact consisting of a first conductive material; a second contact consisting of a second conductive material and connecting a lower end thereof to the upper end of the first contact; and intermediate wiring consisting of a third conductive material, positioning undersides in a part upper than the underside of the first contact, also positioning top faces in the part lower than the top face of the second contact, and being separated from the first and second contacts. The diffusion coefficient of the first conductive material to the second conductive material is smaller than that of the third conductive material to the second conductive material. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其能够使半导体器件的尺寸减小，特别是垂直地连接两个触点。解决方案：半导体器件包括：由第一导电材料组成的第一接触; 第二触点，由第二导电材料组成并将其下端连接到第一触点的上端; 以及由第三导电材料组成的中间布线，其位于比第一接触件的下侧高的部分中的下侧，还将顶面定位在比第二接触件的顶面低的部分中，并且与第一和第二接触部分离。第一导电材料对第二导电材料的扩散系数小于第二导电材料的第三导电材料的扩散系数。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011181891A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011181891A
公开(公告)日：2011-09-15
申请号：JP2010263660
申请日：2010-11-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which the number of upper layer interconnects disposed in peripheral circuit parts can be reduced.
SOLUTION: The nonvolatile semiconductor memory device includes: a substrate 100 provided with a memory cell part and sense amplifiers on a surface thereof; second element isolation regions and second element regions 201 and 202 formed in the substrate below the sense amplifiers; peripheral transistors (gate electrodes) 206 including gate insulating films and gate electrodes formed in order on the second element regions and disposed in the sense amplifiers; a plurality of interconnects 208 disposed in the same layer; and a plurality of bit lines BL disposed on the substrate in the memory cell part and electrically connecting the memory cell part and the sense amplifiers. The second element region includes first and second stripe portions 211 formed like stripes and a connecting portion 212 formed so as to connect the first and second stripe portions and further includes a source contact (C
S1 , C
S2 ) formed on the connecting portion of the second element region and electrically connected to one of the interconnects.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供可以减少设置在外围电路部分中的上层布线数量的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括：在其表面上设置有存储单元部分和读出放大器的基板100; 形成在感测放大器下面的衬底中的第二元件隔离区域和第二元件区域201和202; 外围晶体管（栅电极）206，包括在第二元件区上依次形成的栅极绝缘膜和栅极，并设置在读出放大器中; 布置在同一层中的多个互连208; 以及设置在存储单元部分中的基板上并电连接存储单元部分和读出放大器的多个位线BL。第二元件区域包括形成为条状的第一条纹部分211和第二条纹部分211以及形成为连接第一条纹部分和第二条纹部分的连接部分212，并且还包括源极接触件（C S1 ，C

10. 发明专利

JP2012109450A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：JP2012109450A
公开(公告)日：2012-06-07
申请号：JP2010258011
申请日：2010-11-18
申请人： TOSHIBA CORP
发明人： NODA MITSUHIKO , NAGASHIMA YUKINOBU
IPC分类号： H01L27/115 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/532 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device capable of reducing a delay of a circuit operation in a peripheral circuit.SOLUTION: A non-volatile semiconductor memory device comprises: a plurality of memory cells MC formed on a semiconductor substrate 11 at a predetermined interval from each other, each having a gate insulating film 1, a floating gate electrode 2, an inter-gate insulating film 3 and a control gate 4; a side wall insulating film 18B formed in a side wall of the floating gate 2, in a side wall of the inter-gate insulating film 3, and in a side wall of the control gate electrode 4 of the memory cell MC, and having a cavity; a peripheral transistor PT formed on a substrate 11, and having a gate insulating film 1, a first gate electrode 2, an inter-gate insulating film 3 and a control gate electrode 4; a side wall insulating film 18A formed in a side wall of the first gate electrode 2, in a side wall of the inter-gate insulating film 3, and in a side wall of the control gate electrode 4 of the peripheral transistor PT, and having a cavity 19A. An upper end of the cavity 19A located at the lowest position on the substrate 11 is located at a lower position on the substrate 11 than the inter-gate insulating film 3.

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