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1. 发明专利

JP2012164776A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012164776A
公开(公告)日：2012-08-30
申请号：JP2011023215
申请日：2011-02-04
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , KUTSUKAKE HIROYUKI , ENDO MASATO
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/11519
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which inhibits deterioration in junction breakdown voltage and surface breakdown voltage of a transistor thereby achieving high reliability.SOLUTION: A transistor Tr.2 comprises a source diffusion layer having a high concentration source region 9, a gate electrode having a gate insulation film 16 thicker than a gate insulation film of a memory cell, and a drain diffusion layer 22 having a high concentration drain region 9 and a low concentration drain region 23 surrounding the high concentration drain region 9. The drain diffusion layer 22 has a first depression lower than a bottom face of the gate insulation film 16. The low concentration drain region 23 has a second depression of "c" lower than the first depression, and is connected to bit lines via contacts 10 bonded to the high concentration drain region 9 and connected to a sense amplifier via contacts bonded to the high concentration source region.
摘要翻译：要解决的问题：提供一种抑制晶体管的结击穿电压和表面击穿电压劣化的非易失性半导体存储装置，从而实现高可靠性。解决方案：晶体管Tr2包括具有高浓度源极区9的源极扩散层，具有比存储单元的栅极绝缘膜厚的栅极绝缘膜16的栅电极和具有高浓度漏极区域9和围绕高浓度漏极区域9的低浓度漏极区域23.漏极扩散层22具有比栅极绝缘膜16的底面低的第一凹部。低浓度漏极区域23具有第二按压“c”低于第一凹陷，并且通过接合到高浓度漏极区9的接触10连接到位线，并通过接合到高浓度源区的触点连接到读出放大器。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012099627A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2012099627A
公开(公告)日：2012-05-24
申请号：JP2010245868
申请日：2010-11-02
申请人： Toshiba Corp , 株式会社東芝
发明人： OZAKI TORU , NOGUCHI MITSUHIRO
IPC分类号： H01L27/10 , H01L21/3213 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/0207 , H01L27/11519 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that suppresses an increase in occupied area, and to provide a method of manufacturing the same.SOLUTION: A nonvolatile semiconductor memory device comprises: a first region; a second region; and a plurality of word lines. The first region has a plurality of memory transistors that are electrically rewritable. The second region is located around the first region. The plurality of word lines are each connected to the gates of the plurality of memory transistors. The plurality of word lines each include a wiring portion and a connection portion. The wiring portions extend in a first direction toward the second region from the first region and are arranged with a predetermined distance from one another in a second direction perpendicular to the first direction. The connection portions extend from the wiring portions, are provided in the second region, and are electrically connected to contacts extending in the stacked direction. Ends of the plurality of connection portions are formed along the line extending in the second direction.
摘要翻译：要解决的问题：提供一种抑制占用面积增加的非易失性半导体存储器件，并提供其制造方法。解决方案：非易失性半导体存储器件包括：第一区域; 第二区域和多个字线。第一区域具有可电可重写的多个存储晶体管。第二个地区位于第一个地区周围。多个字线各自连接到多个存储晶体管的栅极。多个字线各自包括布线部分和连接部分。布线部从第一区域沿第一方向朝向第二区域延伸，并且在与第一方向垂直的第二方向上彼此以预定距离布置。连接部分从布线部分延伸，设置在第二区域中，并且电连接到在堆叠方向上延伸的触点。多个连接部的端部沿着沿第二方向延伸的线形成。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012015301A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2012015301A
公开(公告)日：2012-01-19
申请号：JP2010150041
申请日：2010-06-30
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAMI JUNYA , NOGUCHI MITSUHIRO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/11524 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which operational reliability can be enhanced.SOLUTION: The semiconductor memory device comprises: a charge storage layer 14 formed on a semiconductor substrate 10 with a first insulating film 13 interposed therebetween; and a control gate 16 formed on the charge storage layer 14 with a second insulating film 15 interposed therebetween. The control gate 16 has a side face swelling outward in at least a partial region 16-2. In the control gate 16, a height H1 from a portion where the side face begins to swell to the top of the control gate 16 is larger than the maximum width W2_max2 of the control gate 16 in the region above the portion where the side face begins to swell.
摘要翻译：要解决的问题：提供可以提高操作可靠性的半导体存储器件。解决方案：半导体存储器件包括：形成在半导体衬底10上的电荷存储层14，其间插入有第一绝缘膜13; 以及形成在电荷存储层14上的控制栅极16，其间插入有第二绝缘膜15。控制门16具有在至少部分区域16-2中向外膨胀的侧面。在控制门16中，从侧面开始膨胀到控制栅极16的顶部的部分的高度H1大于侧面开始部分上方的区域中的控制栅极16的最大宽度W2_max2 膨胀版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011216837A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011216837A
公开(公告)日：2011-10-27
申请号：JP2010143666
申请日：2010-06-24
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , SAWAMURA KENJI , KAMIGAICHI TAKESHI , ISOBE KATSUAKI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/025 , G11C16/0483 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device with improved operational characteristics and reliability.SOLUTION: The semiconductor memory device includes a memory cell array 1 having a plurality of first memory cell units and second memory cell units each having a plurality of memory cells, plural sets of first wirings, and plural sets of second wirings; a first sense amplifier circuit 462 connected to the plural sets of first wirings; and a second sense amplifier circuit 461 connected to the plural sets of second wirings. Each of the plural sets of first and second wirings is formed with metal embedded therein. All of the first and second wirings have the same height up to the upper surfaces. The plural sets of first and second wirings adjacently formed to each other are repeatedly constituted as a plurality of pairs. At least either of width and thickness in the plural sets of second wirings is smaller than that in the plural sets of first wirings. The first sense amplifier circuit is disposed to face the second sense amplifier circuit with the memory cell array sandwiched therein.
摘要翻译：要解决的问题：提供具有改进的操作特性和可靠性的半导体存储器件。解决方案：半导体存储器件包括具有多个第一存储单元单元的存储单元阵列1和具有多个存储单元的第二存储单元单元多组第一布线和多组第二布线; 连接到多组第一布线的第一读出放大器电路462; 以及连接到多组第二布线的第二读出放大器电路461。多组第一和第二布线中的每一个形成有嵌入其中的金属。所有第一和第二布线具有与上表面相同的高度。彼此相邻形成的多组第一和第二布线被重复地构成为多对。多组第二布线中的宽度和厚度中的至少一个小于多组第一布线中的至少任一个。第一读出放大器电路设置成面对第二读出放大器电路，其中存储单元阵列被夹在其中。

5. 发明专利

JP2010272803A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010272803A
公开(公告)日：2010-12-02
申请号：JP2009125422
申请日：2009-05-25
申请人： Toshiba Corp , 株式会社東芝
发明人： ISHIHARA HANAE , NOGUCHI MITSUHIRO
IPC分类号： H01L27/06 , H01L21/822 , H01L21/8234 , H01L21/8246 , H01L27/04 , H01L27/088 , H01L27/10 , H01L27/105
CPC分类号： H01L28/20 , H01L27/0629 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for simultaneously achieving reduction in size of a resistance element, and improvement in latch-up resistance of a field effect transistor (FET), and also provide a method of manufacturing the same semiconductor device. SOLUTION: A shallow trench isolation (STI) 12 is formed in an N-type well resistance element forming region of a silicon substrate 11. Next, a donor diffusing region 21 is formed by doping donor in a P-type MOS transistor forming region. Next, an N-type well 14 is formed in the region just under the STI 12 in the N-type well resistance element forming region, and a donor diffusing region 20 is also formed in a P-type MOS transistor forming region by doping the donor in the N-type well resistance element forming region and the P-type MOS transistor forming region. The donor diffusing regions 21 and 20 are stacked to form an N-type well 19 constituting a channel region of the P-type MOS transistor 7. In this case, impurity to form an N-type well 14 and the donor diffusing region 20 is less doped than the impurity to form the donor diffusing region 21. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，用于同时实现电阻元件的尺寸减小以及场效应晶体管（FET）的闩锁电阻的提高，并且还提供制造相同半导体的方法设备。解决方案：在硅衬底11的N型阱电阻元件形成区域中形成浅沟槽隔离（STI）12。接下来，通过在P型MOS晶体管中掺杂施主来形成施主漫射区21 形成区域。接下来，在N型阱电阻元件形成区域的STI 12正下方的区域形成有N型阱14，在P型MOS晶体管形成区域中也形成施主漫射区域20， N型阱电阻元件形成区域和P型MOS晶体管形成区域。施主漫射区21和20被堆叠以形成构成P型MOS晶体管7的沟道区的N型阱19.在这种情况下，形成N型阱14和施主漫射区20的杂质为较杂质少掺杂以形成供体扩散区21.版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2009206450A Nonvolatile semiconductor storage device and depletion type mos transistor 有权
标题翻译：非易失性半导体存储器件和漏电型MOS晶体管
公开(公告)号：JP2009206450A
公开(公告)日：2009-09-10
申请号：JP2008050066
申请日：2008-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： GOMIKAWA KENJI , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7838 , H01L27/11526 , H01L27/11534
摘要： PROBLEM TO BE SOLVED: To vary an intrinsic breakdown voltage and a soft breakdown voltage without varying the area of a transistor. SOLUTION: A peripheral circuit for driving a memory cell transistor in a memory cell array includes at least a first transistor. The first transistor includes a gate electrode 26 formed on a surface of a semiconductor substrate 1 with a gate insulating film 25 interposed, a channel region 22 formed right below the gate electrode 26, a source-drain diffusion region 21 formed in a manner of self-matching with the gate electrode 26, and an overlap region 24 formed right below the gate electrode 26 that the channel region 22 and source-drain diffusion region 21 overlap with. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：改变本征击穿电压和软击穿电压，而不改变晶体管的面积。解决方案：用于驱动存储单元阵列中的存储单元晶体管的外围电路至少包括第一晶体管。第一晶体管包括形成在半导体衬底1的表面上的栅电极26，栅极绝缘膜25插入，形成在栅极26正下方的沟道区22，以自我形式形成的源极 - 漏极扩散区21 与栅电极26匹配，以及形成在栅极26正下方的重叠区24，沟道区22和源极 - 漏极扩散区21重叠。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2009141218A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009141218A
公开(公告)日：2009-06-25
申请号：JP2007317582
申请日：2007-12-07
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , GOMIKAWA KENJI
IPC分类号： H01L21/8247 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07 , H03K17/06 , H03K19/00
CPC分类号： G11C16/24 , G11C16/30 , H01L27/0207 , H01L27/0222 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing an increase in a circuit area and improving boosting efficiency. SOLUTION: The semiconductor device comprises device areas AA; a plurality of MOS transistors TR and a capacitive element C formed on the device area AA; a voltage generation circuit 4 connected in series with the plurality of MOS transistors TR connected to the capacitive element C; contact plugs CP4, CP5 formed on at least one area 32 of a source or a drain of the MOS transistor TR; and a memory cell MT storing data. In each of device areas AA, as the position of the MOS transistor TR in the serial connection is located in a more rear stage, the distance a between a gate 34 and the contact plugs CP4, CP5 becomes lager. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够抑制电路面积增加并提高增压效率的半导体器件。解决方案：半导体器件包括器件区域AA; 形成在器件区域AA上的多个MOS晶体管TR和电容元件C; 与连接到电容元件C的多个MOS晶体管TR串联连接的电压产生电路4; 形成在MOS晶体管TR的源极或漏极的至少一个区域32上的接触插塞CP4，CP5; 和存储数据的存储单元MT。在每个器件区域AA中，随着串联连接中的MOS晶体管TR的位置位于更后级，栅极34与接触插头CP4，CP5之间的距离a变大。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2009016444A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2009016444A
公开(公告)日：2009-01-22
申请号：JP2007174280
申请日：2007-07-02
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO TOUSHI , NOGUCHI MITSUHIRO
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/025 , G11C16/0483
摘要： PROBLEM TO BE SOLVED: To improve reliability on a word line by a novel contact hole structure.
SOLUTION: A semiconductor memory according to an embodiment of the present invention has a memory cell array area having memory cells, a word line contact area adjacent to the memory cell array area, word lines disposed across the memory cell array area and word line contact area, contact holes CS1(n-1) provided on word lines 17 and 18 in the word line contact area, and a word line driver connected to the word lines 17 and 18 through the contact holes CS1(n-1). Further, the size of each of the contact holes CS1(n-1) is larger than widths of the word lines 17 and 18 and lowest portions of the contact holes CS1(n-1) are lower than top surfaces of the word lines 17 and 18 and higher than reverse surfaces thereof.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过新颖的接触孔结构提高字线上的可靠性。解决方案：根据本发明的实施例的半导体存储器具有存储单元阵列区域，其具有存储单元，与存储单元阵列区域相邻的字线接触区域，跨过存储单元阵列区域布置的字线和字线接触区域，字线接触区域中的字线17和18上提供的接触孔CS1（n-1）和通过接触孔CS1（n-1）连接到字线17和18的字线驱动器。此外，每个接触孔CS1（n-1）的尺寸大于字线17和18的宽度，并且接触孔CS1（n-1）的最低部分比字线17的顶表面低并且高于其反面。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2008258653A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008258653A
公开(公告)日：2008-10-23
申请号：JP2008157050
申请日：2008-06-16
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , KAJIMOTO SANETOSHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having a double well which is advantageous to microfabrication, and wells separated from the double well.
SOLUTION: The nonvolatile semiconductor storage device includes a first conductive type first well 10 formed in a first conductive type semiconductor substrate 1, a plurality of memory-cell transistors Q5-1, Q5-2 formed in the first well 10, a second conductive type second well, and a second conductive type third well region 5 formed in the semiconductor substrate 1. The second well has a first portion 7 surrounding a side face region of the first well 10, and a second portion 9 surrounding a lower region of the first well 10, and electrically separates the first well 10 from the semiconductor substrate 1.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有双阱的非极性半导体存储装置，其有利于微细加工，并且与双井分离井。解决方案：非易失性半导体存储器件包括形成在第一导电型半导体衬底1中的第一导电类型的第一阱10，形成在第一阱10中的多个存储单元晶体管Q5-1，Q5-2，第二导电类型的第二阱以及形成在半导体衬底1中的第二导电类型的第三阱区5.第二阱具有围绕第一阱10的侧面区域的第一部分7和围绕第一阱10的下部区域的第二部分9 的第一阱10，并且将第一阱10与半导体衬底1电隔离。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2008098313A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008098313A
公开(公告)日：2008-04-24
申请号：JP2006276980
申请日：2006-10-10
申请人： Toshiba Corp , 株式会社東芝
发明人： GOMIKAWA KENJI , SAWAMURA KENJI , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which improves a cut-off characteristic and takes advantage for miniaturization. SOLUTION: The semiconductor memory device comprises a memory cell array 1 provided on a semiconductor substrate, a gate insulating film 13 provided on the semiconductor substrate having a deeper recess structure 15 near only the central part in comparison with the semiconductor substrate having the memory cell array provided thereon, a gate electrode 12 provided on the gate insulating film, and a select transistor ST2 for selecting the memory cell array. COPYRIGHT: (C)2008,JPO&INPIT

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