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1. 发明专利

JP2010080007A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010080007A
公开(公告)日：2010-04-08
申请号：JP2008248664
申请日：2008-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAGAWA MICHIO
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which voltage stress caused in a transfer register for transferring high voltage used during write operation or the like can be relaxed. SOLUTION: A memory cell group which has a plurality of memory cells MC including a floating gate and a control gate and in which current paths of a plurality of memory cells MC are connected in series is formed. Transfer transistors TR0 to TR63 are connected to control gates of memory cells MC of the memory cell group. When voltage VPASS being higher than power source voltage VCC and lower than write voltage VPGM is applied to the control gate of the memory cell of non-selection during write operation, voltage VRDEC being higher than voltage VPASS and not more than write voltage VPGM are applied to the gate of the transfer transistor. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性半导体存储器件，其中可以放宽在写入操作期间使用的用于传送高电压的转移寄存器中引起的电压应力等。解决方案：形成具有包括浮动栅极和控制栅极的多个存储单元MC并且其中多个存储单元MC的电流路径串联连接的存储单元组。传输晶体管TR0至TR63连接到存储单元组的存储单元MC的控制栅极。当在写入操作期间将电压VPASS高于电源电压VCC并低于写入电压VPGM的电压施加到非选择存储单元的控制栅极时，施加高于电压VPASS且不大于写入电压VPGM的电压VRDEC 到转移晶体管的栅极。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2007042166A Nonvolatile semiconductor storage device and method of operating the same 审中-公开
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：JP2007042166A
公开(公告)日：2007-02-15
申请号：JP2005222699
申请日：2005-08-01
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAGAWA MICHIO , SAKUI YASUSHI
IPC分类号： G11C16/02
CPC分类号： G11C16/102 , G11C11/5621 , G11C2216/08
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can exactly control, the threshold value and to provide the method of driving the same. SOLUTION: This nonvolatile semiconductor storage device has an electrically rewritable memory cell which is composed of a laminated floating gate and control gate on the semiconductor layer, and a plurality of threshold variable pulses having a stepwise high potentials with difference of a first voltage which is required for injecting one electron into the floating gate, are respectively impressed on the control gate of the memory cell during a predetermined period. By controlling the number of electrons to be injected to the floating gate, the threshold of the memory cell can be exactly changed while suppressing the expansion of threshold distribution. By this nonvolatile semiconductor storage device, the threshold can be exactly controlled when a multi-valued bit is stored in one memory cell by the especially fine threshold control. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够精确地控制阈值的非易失性半导体存储装置，并提供其驱动方法。解决方案：该非易失性半导体存储器件具有由半导体层上的层叠浮栅和控制栅极构成的电可重写存储单元，以及多个具有逐步高电位的阈值可变脉冲，其具有第一电压在一个预定的时间段内分别将一个电子注入到浮动栅极中所需要的电压施加在存储器单元的控制栅极上。通过控制要注入到浮动栅极的电子数，可以精确地改变存储单元的阈值，同时抑制阈值分布的扩展。通过这种非易失性半导体存储装置，当通过特别精细的阈值控制将多值位存储在一个存储器单元中时，可以精确地控制阈值。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2011154762A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011154762A
公开(公告)日：2011-08-11
申请号：JP2010015731
申请日：2010-01-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , NAKANO TAKESHI , NAKAGAWA MICHIO
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having data erase mode that suppresses deterioration of cell characteristics. SOLUTION: The semiconductor memory device includes: a memory cell array where nonvolatile memory cells are arranged; and an erase voltage generation circuit that generates an erase voltage for erasing data in the memory cell array. In the data erase mode that applies the erase voltage to selected regions in the memory cell array in multiple cycles, a rise waveform of the erase voltage at an initial phase of the multiple erase cycles is less steep than that in subsequent cycles. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有抑制电池特性劣化的数据擦除模式的半导体存储器件。解决方案：半导体存储器件包括：非易失性存储单元布置的存储单元阵列; 以及产生用于擦除存储单元阵列中的数据的擦除电压的擦除电压产生电路。在以多个周期将擦除电压施加到存储单元阵列中的选定区域的数据擦除模式中，多个擦除周期的初始相位处的擦除电压的上升波形不如后续周期那样急剧上升。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2007323782A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007323782A
公开(公告)日：2007-12-13
申请号：JP2006155407
申请日：2006-06-02
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAGAWA MICHIO , NAKAMURA HIROSHI
IPC分类号： G11C16/06
CPC分类号： G11C16/08
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which Vpp can be transferred without voltage drop of Vth (threshold voltage) of a transfer transistor, also processes are decreased and a cost is reduced by using normal LVP (low voltage P type transistor), in a transfer circuit for transferring Vpp selectively or a decode circuit. SOLUTION: A bi-directional diode of which the threshold value is approximately Vdd is inserted between a gate and a drain using the LVP (low voltage P type transistor) instead of HVP (high voltage P type transistor) of a transfer circuit. COPYRIGHT: (C)2008,JPO&INPIT

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