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1. 发明专利

JP2010165942A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010165942A
公开(公告)日：2010-07-29
申请号：JP2009008080
申请日：2009-01-16
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of preventing defective short circuiting between a gate electrode and a contact wire.
SOLUTION: A gate hardmask, the gate electrode 34 and a gate insulating film 33 are formed on a semiconductor substrate 32. An S/D extension 36 is formed after narrowing a line width of the gate hardmask more than that of the gate electrode. A silicon oxide film is deposition-formed on the whole face, and an insulating member 37 is formed by etching-back, to remain continuously over on one part of an upper face from a sidewall of the gate electrode. A contact junction 38 is formed by using, as masks, the gate electrode and the insulating member, after removing the hardmask. A silicon nitride film 40 and an interlayer insulating film 41 are sequentially deposition-formed, after forming a metal silicide film. A contact hole is formed in the interlayer insulating film, the contact hole is hole-opened followed thereto, by removing the silicon nitride film by anisotropic etching having a high selection ratio to the silicon oxide film, and the contact wire 43 is formed thereby.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，能够防止栅电极和接触导线之间的短路不良。解决方案：栅极硬掩模，栅电极34和栅极绝缘膜33形成在半导体衬底32上。在栅极硬掩模的线宽比栅极更窄之后形成S / D延伸部36 电极。在整个面上沉积形成氧化硅膜，通过蚀刻形成绝缘构件37，从栅电极的侧壁连续地保持在上表面的一部分上。在去除硬掩模之后，通过使用栅电极和绝缘构件作为掩模来形成接触接点38。在形成金属硅化物膜之后，依次沉积氮化硅膜40和层间绝缘膜41。在层间绝缘膜中形成接触孔，通过与氧化硅膜的选择比高的各向异性蚀刻去除氮化硅膜，接着孔开孔，由此形成接触线43。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2006332123A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006332123A
公开(公告)日：2006-12-07
申请号：JP2005149741
申请日：2005-05-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI , HARAKAWA HIDEAKI
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/3065 , H01L21/76 , H01L27/088 , H01L29/423 , H01L29/49
CPC分类号： H01L21/76224 , H01L21/31144 , H01L21/32139 , H01L21/823437
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for suppressing the adhesion of a reaction product on the sidewall of a mask material by etching regardless of the density of a pattern.
SOLUTION: In the manufacturing method of a semiconductor device, mask materials 70, 80 to be patterned on a desired target pattern are deposited on a ground material 10, the mask material is patterned on a spare pattern that contains a target pattern and is wider than it, the mask material is patterned on the target pattern, and a ground material is treated by using the mask material as a mask.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过蚀刻来抑制反应产物在掩模材料的侧壁上的粘附的半导体器件的制造方法，而不管图案的密度如何。解决方案：在半导体器件的制造方法中，要在所需目标图案上图案化的掩模材料70,80沉积在研磨材料10上，掩模材料在包含目标图案的备用图案上被图案化，比其宽，掩模材料在目标图案上图案化，并且通过使用掩模材料作为掩模来处理研磨材料。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2005244009A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005244009A
公开(公告)日：2005-09-08
申请号：JP2004053165
申请日：2004-02-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI , HARAKAWA HIDEAKI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To suppress the abnormal growth of a silicide film on the upper side face of a gate electrode. SOLUTION: The gate electrode 12 including silicon is formed on a semiconductor substrate 10 through a gate insulating film 11. An offset spacer 13 consisting of a silicon oxide film is formed on the side face of the gate electrode 12. A low-concentration impurity layer 14 is formed by using the offset spacer 13 and the gate electrode 12 as masks. The upper surface of the offset spacer 13 is retreated. A sidewall spacer 16 is formed on the side face of the gate electrode 12 and the side face of the offset spacer 13. A high-concentration impurity layer 18 is formed on the surface of a semiconductor substrate 10 by using the sidewall spacer 16, the offset spacer 13 and the gate electrode 12 as masks. A solution which can selectively remove silicon oxide and does not remove the sidewall spacer 16 is supplied to the surface of the semiconductor substrate 10. A metallic layer 19 is stacked to the surface of the semiconductor substrate 10. The gate electrode 12 and the metallic layer 19 are allowed to react to each other to form a silicide film 20. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：抑制栅电极的上侧面上的硅化物膜的异常生长。解决方案：包括硅的栅电极12通过栅极绝缘膜11形成在半导体衬底10上。在栅电极12的侧面上形成由氧化硅膜构成的偏移间隔物13。通过使用偏移间隔物13和栅电极12作为掩模形成浓度杂质层14。偏移间隔件13的上表面被退回。在栅电极12的侧面和偏移间隔物13的侧面上形成侧壁间隔件16.通过使用侧壁间隔件16，在半导体基板10的表面上形成高浓度杂质层18，偏移间隔物13和栅电极12作为掩模。可以选择性地去除氧化硅并且不去除侧壁间隔物16的解决方案被提供给半导体衬底10的表面。金属层19堆叠在半导体衬底10的表面上。栅电极12和金属层 19被允许彼此反应以形成硅化物膜20.版权所有：（C）2005，JPO＆NCIPI

4. 发明专利

JP2012119381A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2012119381A
公开(公告)日：2012-06-21
申请号：JP2010265371
申请日：2010-11-29
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L27/14 , H01L27/146
CPC分类号： H01L27/14632 , H01L21/76898 , H01L23/481 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To ensure the insulation properties between a semiconductor layer and a through electrode even if a through-hole insulating layer retracts from a surface of the semiconductor layer.SOLUTION: A through electrode 9 is buried in a through hole 6 via through-hole insulating layers 7 and 8. The through-hole insulating layers 7 and 8 are formed so as to retract from a surface of a semiconductor layer 3. A recess 10 corresponding to the retraction portion of the through-hole insulating layers 7 and 8 is formed between the semiconductor layer 3 and the through electrode 9. A side-wall insulating film 12 buried in the recess 10 is formed on the side walls of the through electrode 9.
摘要翻译：要解决的问题：即使通孔绝缘层从半导体层的表面缩回，也可以确保半导体层和贯通电极之间的绝缘性。解决方案：通孔绝缘层7和8将通孔9埋入通孔6中。通孔绝缘层7和8形成为从半导体层3的表面缩回。在半导体层3和贯通电极9之间形成有与通孔绝缘层7,8的退避部相对应的凹部10.埋设在凹部10内的侧壁绝缘膜12形成在通孔电极9.版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012004172A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012004172A
公开(公告)日：2012-01-05
申请号：JP2010135177
申请日：2010-06-14
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/768 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing occurrence of a short circuit, and to provide a method of manufacturing the same.SOLUTION: The semiconductor device comprises: a semiconductor substrate; a pair of impurity diffusion regions provided at the predetermined interval on the semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a pair of insulated sidewall spacers covering the both side surfaces of the gate electrode and the both side surfaces of the gate insulating film; and a silicide metal film formed on the top surface of the gate electrode. Each of the sidewall spacers includes an upper sidewall spacer and a lower sidewall spacer that are stacked above and below.
摘要翻译：要解决的问题：提供一种能够防止发生短路的半导体器件，并提供其制造方法。解决方案：半导体器件包括：半导体衬底; 一对在所述半导体衬底上以预定间隔设置的杂质扩散区; 形成在半导体衬底上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 覆盖栅电极的两侧表面和栅极绝缘膜的两个侧表面的一对绝缘侧壁间隔物; 以及形成在栅电极的顶表面上的硅化金属膜。每个侧壁间隔件包括在上部和下部堆叠的上部侧壁间隔件和下部侧壁间隔件。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2008205121A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205121A
公开(公告)日：2008-09-04
申请号：JP2007038327
申请日：2007-02-19
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI , HARAKAWA HIDEAKI
IPC分类号： H01L21/822 , H01L21/768 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088
CPC分类号： H01L27/0629 , H01L28/60 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a proper contact processing method for a semiconductor device which is equipped with a transistor and a capacitor.
SOLUTION: The semiconductor device comprises the transistor including a gate insulating film 131 and a gate electrode 132 formed of an electrode layer 123A; the capacitor including a first capacitor electrode 141 formed of the electrode layer, first capacitor insulation film formed on the first capacitor electrode, a second capacitor electrode 143 formed on the first capacitor insulation film, a second capacitor insulating film formed on the second capacitor electrode, and third capacitor electrode 145 formed on the second capacitor insulating film; a contact plug 201 for the transistor; a contact plug 202 for the first capacitor electrode; a contact plug 203 for the second capacitor electrode; and a wiring pattern 211, in contact with the third capacitor electrode.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为配备有晶体管和电容器的半导体器件提供适当的接触处理方法。解决方案：半导体器件包括晶体管，其包括栅极绝缘膜131和由电极层123A形成的栅电极132; 电容器包括由电极层形成的第一电容器电极141，形成在第一电容器电极上的第一电容器绝缘膜，形成在第一电容器绝缘膜上的第二电容器电极143，形成在第二电容器电极上的第二电容器绝缘膜，和形成在第二电容绝缘膜上的第三电容器电极145; 用于晶体管的接触插头201; 用于第一电容器电极的接触插塞202; 用于第二电容器电极的接触插头203; 以及与第三电容器电极接触的布线图案211。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007184320A Semiconductor device and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007184320A
公开(公告)日：2007-07-19
申请号：JP2006000124
申请日：2006-01-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI
IPC分类号： H01L27/08 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which transistor characteristics can be enhanced by suppressing generation of junction leakage current, and to provide its fabrication process.
SOLUTION: The semiconductor device comprises: a trench 40 formed selectively in the surface portion of a semiconductor substrate 10; a sidewall insulating film 60 formed on the inner side face at the upper portion of the trench; insulating films 50 and 80 formed to fill the trench where the sidewall insulating film is formed; a gate electrode 140 formed on the semiconductor substrate through a gate insulating film 130 in an element region 100 isolated by the sidewall insulating film and the insulating film filling the trench; a gate electrode sidewall 160 formed on the side face of the gate electrode; and a source region and drain region 150 and 170 formed on the opposite sides of a channel region 230 located under the gate electrode contiguously to the trench.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供通过抑制结漏电流的产生而提高晶体管特性并提供其制造工艺的半导体器件。解决方案：半导体器件包括：选择性地形成在半导体衬底10的表面部分中的沟槽40; 形成在沟槽上部的内侧面上的侧壁绝缘膜60; 形成为填充形成侧壁绝缘膜的沟槽的绝缘膜50和80; 通过栅极绝缘膜130形成在半导体衬底上的栅电极140，该绝缘膜130由侧壁绝缘膜隔离的元件区域100和填充沟槽的绝缘膜; 形成在栅电极的侧面上的栅电极侧壁160; 以及源极区域和漏极区域150和170，其形成在位于沟槽区域230的与沟槽连续的下方的相对侧上。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2007149921A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007149921A
公开(公告)日：2007-06-14
申请号：JP2005341607
申请日：2005-11-28
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI , HARAKAWA HIDEAKI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/78
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823878
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a metal silicide film with more uniform thickness than the prior art in an active region, and to provide a manufacturing method of such a semiconductor device.
SOLUTION: The manufacturing method of the semiconductor device comprises a step of forming an element isolation region 20 on a semiconductor substrate 10, forming an impurity diffusion layer 70 in an active region AA adjacent to the element isolation region, depositing a metal film 80 on the semiconductor substrate, removing at least a partial metal film on the element isolation region, and forming a silicide film 110 on the active region in a self alignment manner by subjecting the metal film and the semiconductor substrate to heat treatment.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其包括在有源区中具有比现有技术更厚的厚度的金属硅化物膜，并提供这种半导体器件的制造方法。解决方案：半导体器件的制造方法包括在半导体衬底10上形成元件隔离区20的步骤，在与元件隔离区相邻的有源区AA中形成杂质扩散层70，沉积金属膜 80，去除元件隔离区域上的至少一部分金属膜，并且通过对金属膜和半导体基板进行热处理，以自对准的方式在有源区上形成硅化物膜110。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2003179059A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003179059A
公开(公告)日：2003-06-27
申请号：JP2001378778
申请日：2001-12-12
申请人： TOSHIBA CORP
发明人： HASUNUMA MASAHIKO , SAKATA ATSUKO , KOMUKAI TOSHIAKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To improve reliability by improving barrier property and intensity of a barrier film at a wiring pad. SOLUTION: An interlayer dielectric 3, a diffusion barrier insulation film 4 and a Cu wiring 5 are layered in a plurality of layers on a Si substrate 2 in the multilayer wiring structure. Pair of Ta 2 N layer 11 and Ta layer area alternately and continuously formed in two pairs or more on the surface of Cu wiring 5a of the pad of a semiconductor device 1 and a barrier metal film 13 of pad in the composite lamination structure is also provided. In addition, an Al cap film 14 is provided on the surface of film 13 to form a wiring pad 8a. COPYRIGHT: (C)2003,JPO

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