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1. 发明专利

JP2013162076A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013162076A
公开(公告)日：2013-08-19
申请号：JP2012025092
申请日：2012-02-08
申请人： Toshiba Corp , 株式会社東芝
发明人： HARAKAWA HIDEAKI
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/105 , H01L29/78 , H01L29/82 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To achieve microfabrication of a cell size and high performance of a Fin-FET.SOLUTION: A semiconductor device includes a semiconductor substrate 10, a gate electrode 20, a first semiconductor layer 25a, and a second semiconductor layer 25b. The semiconductor substrate has a substrate portion 8, a first fin portion 9a on the substrate portion, and a second fin portion 9b adjacent to the first fin portion. The gate electrode is formed by connecting side surfaces and a part of top surfaces of the first fin portion and the second fin portion in a channel region via an insulating layer. The first semiconductor layer and the second semiconductor layer are formed on the side surfaces and a part of the top surfaces of the first fin portion and the second fin portion in a source/drain region, respectively. The height of the top surface of the first fin portion is higher than that of the top surface of the second fin portion.
摘要翻译：要解决的问题：实现Fin-FET的电池尺寸和高性能的微细加工。解决方案：半导体器件包括半导体衬底10，栅电极20，第一半导体层25a和第二半导体层25b。半导体衬底具有衬底部分8，衬底部分上的第一鳍片部分9a和邻近第一鳍片部分的第二鳍片部分9b。栅极通过绝缘层将沟道区域中的侧表面和第一鳍片部分和第二鳍片部分的顶表面的一部分连接而形成。第一半导体层和第二半导体层分别形成在源极/漏极区域中的第一鳍片部分和第二鳍片部分的侧表面和顶表面的一部分上。第一翅片部分的顶表面的高度高于第二翅片部分的顶表面的高度。

2. 发明专利

JP2006332123A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006332123A
公开(公告)日：2006-12-07
申请号：JP2005149741
申请日：2005-05-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI , HARAKAWA HIDEAKI
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/3065 , H01L21/76 , H01L27/088 , H01L29/423 , H01L29/49
CPC分类号： H01L21/76224 , H01L21/31144 , H01L21/32139 , H01L21/823437
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for suppressing the adhesion of a reaction product on the sidewall of a mask material by etching regardless of the density of a pattern.
SOLUTION: In the manufacturing method of a semiconductor device, mask materials 70, 80 to be patterned on a desired target pattern are deposited on a ground material 10, the mask material is patterned on a spare pattern that contains a target pattern and is wider than it, the mask material is patterned on the target pattern, and a ground material is treated by using the mask material as a mask.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过蚀刻来抑制反应产物在掩模材料的侧壁上的粘附的半导体器件的制造方法，而不管图案的密度如何。解决方案：在半导体器件的制造方法中，要在所需目标图案上图案化的掩模材料70,80沉积在研磨材料10上，掩模材料在包含目标图案的备用图案上被图案化，比其宽，掩模材料在目标图案上图案化，并且通过使用掩模材料作为掩模来处理研磨材料。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006295071A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2006295071A
公开(公告)日：2006-10-26
申请号：JP2005117304
申请日：2005-04-14
申请人： Toshiba Corp , 株式会社東芝
发明人： HARAKAWA HIDEAKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can control the variation of a gate threshold and can inhibit the increase of parasitic resistance causing the reduction of an amount of a driving current.
SOLUTION: The method includes a process to deposit a gate insulating film 3 on a semiconductor substrate 1, a process to form a gate electrode 4 on the gate insulating film 3, a process to deposit insulating films 5, 6 to cover the gate electrode 4, a process to remove part of the insulating films 5, 6 by anisotropic etching so that the semiconductor substrate 1 is not exposed, a process to remove part of the insulating films 5, 6 by isotropic etching to form spacers 5, 6 on the side wall of the gate electrode 4, a process to expose the semiconductor substrate 1, and a process to form semiconductor areas 7a-7d by implanting an impurity ion into the semiconductor substrate 1 using the gate electrode 4 and spacers 5, 6 as a mask and carrying out heat treatment.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件制造方法，其可以控制栅极阈值的变化并且可以抑制寄生电阻的增加，从而导致驱动电流的量的减少。解决方案：该方法包括在半导体衬底1上沉积栅极绝缘膜3的工艺，在栅极绝缘膜3上形成栅电极4的工艺，沉积绝缘膜5,6的工艺，以覆盖栅电极4，通过各向异性蚀刻去除部分绝缘膜5,6以使半导体衬底1不被暴露的工艺，通过各向同性蚀刻去除部分绝缘膜5,6以形成间隔物5,6的工艺在栅电极4的侧壁上，暴露半导体衬底1的工艺，以及通过使用栅电极4和间隔物5,6将杂质离子注入到半导体衬底1中以形成半导体区域7a-7d的工艺为面具进行热处理。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005244009A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005244009A
公开(公告)日：2005-09-08
申请号：JP2004053165
申请日：2004-02-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMUKAI TOSHIAKI , HARAKAWA HIDEAKI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To suppress the abnormal growth of a silicide film on the upper side face of a gate electrode. SOLUTION: The gate electrode 12 including silicon is formed on a semiconductor substrate 10 through a gate insulating film 11. An offset spacer 13 consisting of a silicon oxide film is formed on the side face of the gate electrode 12. A low-concentration impurity layer 14 is formed by using the offset spacer 13 and the gate electrode 12 as masks. The upper surface of the offset spacer 13 is retreated. A sidewall spacer 16 is formed on the side face of the gate electrode 12 and the side face of the offset spacer 13. A high-concentration impurity layer 18 is formed on the surface of a semiconductor substrate 10 by using the sidewall spacer 16, the offset spacer 13 and the gate electrode 12 as masks. A solution which can selectively remove silicon oxide and does not remove the sidewall spacer 16 is supplied to the surface of the semiconductor substrate 10. A metallic layer 19 is stacked to the surface of the semiconductor substrate 10. The gate electrode 12 and the metallic layer 19 are allowed to react to each other to form a silicide film 20. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：抑制栅电极的上侧面上的硅化物膜的异常生长。解决方案：包括硅的栅电极12通过栅极绝缘膜11形成在半导体衬底10上。在栅电极12的侧面上形成由氧化硅膜构成的偏移间隔物13。通过使用偏移间隔物13和栅电极12作为掩模形成浓度杂质层14。偏移间隔件13的上表面被退回。在栅电极12的侧面和偏移间隔物13的侧面上形成侧壁间隔件16.通过使用侧壁间隔件16，在半导体基板10的表面上形成高浓度杂质层18，偏移间隔物13和栅电极12作为掩模。可以选择性地去除氧化硅并且不去除侧壁间隔物16的解决方案被提供给半导体衬底10的表面。金属层19堆叠在半导体衬底10的表面上。栅电极12和金属层 19被允许彼此反应以形成硅化物膜20.版权所有：（C）2005，JPO＆NCIPI

5. 发明专利

JP2013243307A Semiconductor manufacturing apparatus and semiconductor device manufacturing method 审中-公开
标题翻译：半导体制造设备和半导体器件制造方法
公开(公告)号：JP2013243307A
公开(公告)日：2013-12-05
申请号：JP2012116783
申请日：2012-05-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SETO AKISHI , HARAKAWA HIDEAKI
IPC分类号： H01L21/302 , H01J37/305 , H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08 , H01L43/12
CPC分类号： H01L21/2633 , H01L27/222 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus and a semiconductor device manufacturing method, which can inhibit reattachment from adhesion on a lateral face of a memory element even when an aspect ratio of the memory element is increased.SOLUTION: A semiconductor manufacturing apparatus according to a present embodiment comprises: a stage which can mount a semiconductor substrate; a first irradiation part for radiating etching beams from a first direction that inclines at any angle from a vertical direction of a surface of the semiconductor substrate; and a second irradiation part for radiating etching beams from a second direction that inclines at any angle from the vertical direction. The first and second irradiation parts radiate etching beams simultaneously when the semiconductor substrate or a material on the semiconductor substrate is processed.
摘要翻译：要解决的问题：提供一种半导体制造装置和半导体器件制造方法，其即使当存储元件的纵横比增加时也可以抑制重新附着在存储元件的侧面上的粘附。解决方案：半导体制造装置根据本实施例包括：可安装半导体衬底的平台; 第一辐射部分，用于从与半导体衬底的表面的垂直方向成任意角度倾斜的第一方向辐射蚀刻光束; 以及第二照射部分，用于从与垂直方向成任意角度倾斜的第二方向辐射蚀刻光束。当处理半导体衬底或半导体衬底上的材料时，第一和第二照射部分同时辐射蚀刻光束。

6. 发明专利

JP2011040578A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011040578A
公开(公告)日：2011-02-24
申请号：JP2009186780
申请日：2009-08-11
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA HISASHI , HARAKAWA HIDEAKI
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses a decrease of process margin of lithography when forming a pair of MISFETs each of which includes a gate electrode of different thickness and a channel type different with each other.
SOLUTION: The semiconductor device includes: a semiconductor substrate 100 which includes a first region P including a semiconductor region with a first main surface, a second region N including the semiconductor region with a second main surface and whose first main surface is lower than the second main surface; a first conductivity-type MISFET which is disposed in the first region P and which includes first gate electrodes 108, 109; and a second conductivity-type MISFET which is disposed in the second region N and which includes a second gate electrode 109. In the semiconductor device, there is provided the second conductivity-type MISFET where the thickness of the second gate electrode 109 is thinner than that of each of the first gate electrode 108, 109 so that the height of an upper surface of the second gate electrode 109 and that of the first gate electrode 108, 109 are the same.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其在形成一对MISFET时抑制光刻的工艺余量的降低，每个MISFET包括不同厚度的栅电极和彼此不同的沟道类型。解决方案：半导体器件包括：半导体衬底100，其包括第一区域P，第一区域P包括具有第一主表面的半导体区域，第二区域N包括具有第二主表面并且第一主表面较低的半导体区域比第二主表面; 第一导电型MISFET，其设置在第一区域P中并且包括第一栅电极108,109; 以及第二导电型MISFET，其设置在第二区域N中并且包括第二栅电极109.在半导体器件中，提供第二导电型MISFET，其中第二栅电极109的厚度比第一栅电极108,109中的每一个的高度使得第二栅电极109的上表面和第一栅电极108,109的上表面的高度相同。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2007207816A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2007207816A
公开(公告)日：2007-08-16
申请号：JP2006021998
申请日：2006-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA HISASHI , HARAKAWA HIDEAKI , NOMACHI EIKO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/283 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily increase the thickness of a stress application film, and to provide a method of manufacturing the semiconductor device.
SOLUTION: The semiconductor device is provided with, as shown in Fig. 2H, a semiconductor substrate 101, a gate insulation film 102A, a gate electrode 102B, a gate side wall insulation film, an interlayer insulation film 112, a wiring layer, an interlayer connection part, and a stress application film. The stress application film has a first section arranged between the semiconductor substrate 101 and the interlayer insulation film 112, a second section arranged between the gate electrode 102B and the interlayer insulation film 112, a third section arranged between the gate side wall insulation film 104 and the interlayer insulation film 112, and a fourth section arranged between the inner face of a through-hole and the interlayer connection part. The stress appliction film applies stress to the semiconductor substrate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种可以容易地增加应力施加膜的厚度的半导体器件，并且提供一种制造半导体器件的方法。解决方案：半导体器件如图1所示。 2H，半导体基板101，栅极绝缘膜102A，栅极电极102B，栅极侧壁绝缘膜，层间绝缘膜112，布线层，层间连接部以及应力施加膜。应力施加膜具有布置在半导体衬底101和层间绝缘膜112之间的第一部分，布置在栅电极102B和层间绝缘膜112之间的第二部分，布置在栅极侧壁绝缘膜104和层间绝缘膜112和布置在通孔的内表面和层间连接部之间的第四部分。应力应力膜对半导体衬底施加应力。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006041118A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006041118A
公开(公告)日：2006-02-09
申请号：JP2004217561
申请日：2004-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： HARAKAWA HIDEAKI
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823864
摘要： PROBLEM TO BE SOLVED: To improve mobility of a carrier in a pMISFET and an nMISFET. SOLUTION: A semiconductor device has a CMISFET comprising an nMISFET and a pMISFET. The nMISFET comprises a first gate electrode 14b and a first spacer 15, including compression stress formed on the side face of this first gate electrode. The pMISFET comprises a second gate electrode 14a and a second spacer 16 of which compression stress is smaller than that of the first spacer 15, formed on a side face of this second gate electrode. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高pMISFET和nMISFET中载流子的迁移率。解决方案：半导体器件具有包括nMISFET和pMISFET的CMISFET。 nMISFET包括第一栅极电极14b和第一间隔物15，其包括形成在该第一栅电极的侧面上的压缩应力。 pMISFET包括形成在该第二栅电极的侧面上的压电应力小于第一间隔物15的第二栅电极14a和第二间隔件16。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2013197413A Method of manufacturing magnetoresistive effect element 审中-公开
标题翻译：制造磁电效应元件的方法
公开(公告)号：JP2013197413A
公开(公告)日：2013-09-30
申请号：JP2012064452
申请日：2012-03-21
申请人： Toshiba Corp , 株式会社東芝
发明人： HARAKAWA HIDEAKI
IPC分类号： H01L43/12 , H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To avoid processing damage.SOLUTION: In the method of manufacturing a magnetoresistive effect element, a first insulation layer 32 and a second insulation layer 33 are formed on a substrate. A second hole 34 penetrating the second insulation layer, and a first hole 35 penetrating the first insulation layer are formed. Diameter of the first hole is set larger than that of the second hole. A first magnetic layer 37 is formed on the substrate in the first hole, and the second insulation layer on the outside of the first and second holes, so as to be separated from each other. Diameters of the first hole and second hole are enlarged. The first magnetic layer on the outside of the first and second holes is removed. On the first magnetic layer in the first hole, a tunnel barrier layer 38 is formed to cover the first magnetic layer in the first hole. A second magnetic layer 39 is formed on the tunnel barrier layer in the first hole.
摘要翻译：要解决的问题：避免加工损坏。解决方案：在制造磁阻效应元件的方法中，在基板上形成第一绝缘层32和第二绝缘层33。形成贯穿第二绝缘层的第二孔34和贯穿第一绝缘层的第一孔35。第一孔的直径设定为比第二孔的直径大。在第一孔中的基板上形成第一磁性层37，在第一孔和第二孔的外侧形成第二绝缘层，以便彼此分离。第一孔和第二孔的直径被扩大。去除第一和第二孔的外侧上的第一磁性层。在第一孔中的第一磁性层上形成隧道势垒层38以覆盖第一孔中的第一磁性层。在第一孔中的隧道势垒层上形成第二磁性层39。

10. 发明专利

JP2013143548A Manufacturing method for magnetic memory 审中-公开
标题翻译：磁记忆的制造方法
公开(公告)号：JP2013143548A
公开(公告)日：2013-07-22
申请号：JP2012004248
申请日：2012-01-12
申请人： Toshiba Corp , 株式会社東芝
发明人： YOSHIKAWA MASAHISA , SEDO SATOSHI , HARAKAWA HIDEAKI
IPC分类号： H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To achieve an exposure step of a magnetic storage element with excellent controllability.SOLUTION: A manufacturing method for magnetic memory includes the steps of: forming a magnetic storage element film 41 on a lower electrode 40; forming a mask layer 42 on the magnetic storage element film 41; processing the magnetic storage element film 41 using the mask layer 42; covering the processed magnetic storage element film 41 by a protection film 43; forming a high ionization rate film 44 on the protection film 43; depositing an interlayer insulating film 25 on the high ionization rate film 44; exposing the high ionization rate film 44 by thinning the interlayer insulating film 25; exposing the mask layer 42 by etching the high ionization rate film 44 and the protection film 43; and forming an upper electrode 45 on the mask layer 42.
摘要翻译：要解决的问题：实现具有优异的可控性的磁存储元件的曝光步骤。解决方案：一种磁存储器的制造方法，包括以下步骤：在下电极40上形成磁存储元件膜41; 在磁存储元件膜41上形成掩模层42; 使用掩模层42处理磁存储元件膜41; 用保护膜43覆盖处理后的磁存储元件膜41; 在保护膜43上形成高电离率膜44; 在高电离率膜44上沉积层间绝缘膜25; 通过使层间绝缘膜25变薄而暴露高电离率膜44; 通过蚀刻高电离率膜44和保护膜43来暴露掩模层42; 并在掩模层42上形成上电极45。

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