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1. 发明专利

JP2012069693A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012069693A
公开(公告)日：2012-04-05
申请号：JP2010212629
申请日：2010-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAMURA TOKUHIDE
IPC分类号： H01L29/78 , H01L21/76
摘要： PROBLEM TO BE SOLVED: To simultaneously achieve high breakdown voltage and reduced on-resistance of a power device.SOLUTION: A semiconductor device comprises: source regions 107A, a drain region 107B, and a drift region 105 adjacent to the drain region 107B in a semiconductor substrate 101; shallow trench isolation (STI) insulating layers I-2 in the drift region 105 between the source regions 107A and the drain region 107B; and gate electrodes 110 on the STI insulating layers I-2, on the drift region 105, and on channel regions between the source regions 107A and the drain region 107B. The STI insulating layers I-2 comprise first oxide films 102 and nitride films 103 on the inner surfaces of a first and second trenches, and second oxide films 104 on the nitride films 103 which fill the first and second trenches. The second trenches are formed in the first trenches, have bottom surfaces lower than those of the first trenches, and have widths narrower than those of the first trenches.
摘要翻译：要解决的问题：同时实现功率器件的高击穿电压和降低的导通电阻。解决方案：半导体器件包括：源极区107A，漏极区107B和与半导体衬底101中的漏极区107B相邻的漂移区105; 在源极区域107A和漏极区域107B之间的漂移区域105中的浅沟槽隔离（STI）绝缘层I-2; 在STI绝缘层I-2上，漂移区105上的栅电极110以及源极区107A和漏极区107B之间的沟道区上。 STI绝缘层I-2包括在第一和第二沟槽的内表面上的第一氧化物膜102和氮化物膜103，以及填充第一和第二沟槽的氮化物膜103上的第二氧化物膜104。第二沟槽形成在第一沟槽中，具有比第一沟槽低的底表面，并且具有比第一沟槽窄的宽度。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012069691A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012069691A
公开(公告)日：2012-04-05
申请号：JP2010212558
申请日：2010-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUCHI TOMOHIRO , HIGUCHI KAZUTO , TOJO HIROSHI , HONNA MASARU , TSUKAMOTO TEPPEI , KITAMURA TOKUHIDE
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L2224/05644 , H01L2224/45 , H01L2224/45147 , H01L2224/48 , H01L2224/48463 , H01L2224/48844 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being efficiently manufactured with regard to bonding using a Cu wire, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device comprises: a Cu electrode pad 3 formed on a substrate 2; an Au metal layer 4 provided so as to cover the electrode pad 3; and a Cu wire 5 bonded on the metal layer 4.
摘要翻译：要解决的问题：提供一种能够使用Cu线进行接合而能够有效地制造的半导体器件，并提供其制造方法。解决方案：半导体器件包括：形成在衬底2上的Cu电极焊盘3; 设置为覆盖电极焊盘3的Au金属层4; 以及结合在金属层4上的Cu线5.版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2010135634A Method for manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2010135634A
公开(公告)日：2010-06-17
申请号：JP2008311273
申请日：2008-12-05
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAMURA TOKUHIDE
IPC分类号： H01L21/306 , B81B3/00 , B81C1/00 , H01H49/00 , H01H59/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having movable portions with high reliability, and the semiconductor device.
SOLUTION: Upper driving electrodes 23 connected to supports 21 and an upper capacitance electrode 25 are extended in a beam shape through silicon nitride films 27. In other words, the silicon nitride films 27 are formed contacting with each upper surface of an end portion of the upper driving electrode 23 and an end portion of the upper capacitance electrode 25 which are separated and faced, and provided approximately parallel to the upper driving electrodes 23 and the upper capacitance electrode 25. The silicon nitride films 27 are formed by being deposited on an upper surface of a conductive film to be formed into the upper driving electrodes 23 and the upper capacitance electrode 25 in a continuous process by a CVD method, and, thereafter, by being patterned by a RIE method. The silicon nitride films 27 are formed so as to have less discontinuity and unevenness in film thickness or film property, and good adhesiveness to the upper driving electrodes 23 and the upper capacitance electrode 25.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种制造具有高可靠性的可移动部分的半导体器件的方法和半导体器件。解决方案：连接到支撑件21的上驱动电极23和上电容电极25通过氮化硅膜27以波束形状延伸。换句话说，氮化硅膜27形成为与端部的每个上表面接触上部驱动电极23的一部分和上部电容电极25的端部分开面对，大致平行于上部驱动电极23和上部电容电极25.氮化硅膜27通过沉积形成在通过CVD方法的连续工艺中形成上驱动电极23和上电容电极25的导电膜的上表面上，然后通过RIE方法图案化。氮化硅膜27形成为具有较小的膜厚度或膜特性的不连续性和不均匀性，并且对上部驱动电极23和上部电容电极25具有良好的粘附性。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JPH11162993A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11162993A
公开(公告)日：1999-06-18
申请号：JP34196597
申请日：1997-11-28
申请人： TOSHIBA CORP
发明人： KITAMURA TOKUHIDE
IPC分类号： H01L29/808 , H01L21/337
摘要： PROBLEM TO BE SOLVED: To provide a junction type of filed effect transistor(JFET) which is made into high breakdown strength, so that a conductive channel region being a low-concentration region may not bump against an impurity diffused region in high concentration, and its manufacture. SOLUTION: In a JFET, a source region 22 and a drain region 23 are separated. A conductive channel region 30 is made along a main surface of a semiconductor substrate 1, on the source/drain regions 22 and 23 and a gate region 21 made apart from each of them. Since a conductive channel region does not have a gate region (high-concentration impurities diffused region) conventionally made on the main surface of a semiconductor substrate, the conductive region does not bump against the high-concentration region, so the breakdown strength between the gate and the drain (or source) can be made into high breakdown strength.

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