专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009099726A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009099726A
公开(公告)日：2009-05-07
申请号：JP2007269039
申请日：2007-10-16
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , Toshiba Joho System Technology Kk , 東芝情報システムテクノロジー株式会社 , 東芝情報システム株式会社 , 株式会社東芝
发明人： HIYAMA KAORU , FUJII OSAMU , SAWADA TATSURO
IPC分类号： H01L21/8238 , H01L21/768 , H01L23/522 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/823807 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a small semiconductor device having high drive power; and to provide its manufacturing method. SOLUTION: In the semiconductor device 1, pMOSs 8 are formed in a pMOS region Rp of a silicon substrate 2, and nMOSs 9 are formed in an nMOS region Rn. Then, a compressive stress film 11 with compressive stress generated therein is formed to cover the pMOS region Rp, a buffer film 13 is formed on an end-side surface of the compressive stress film 11 on the nMOS region Rn side, and a tensile stress film 12 with tensile stress generated therein is formed to cover the nMOS region Rn, an end of the compressive stress film 11 and the buffer film 13. The value of the internal stress of the buffer film 13 is set smaller than the value of the compressive stress of the compressive stress film 11, and the value of the tensile stress of the tensile stress film 12. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有高驱动功率的小型半导体器件; 并提供其制造方法。解决方案：在半导体器件1中，pMOS 8形成在硅衬底2的pMOS区域Rp中，并且nMOS 9形成在nMOS区域Rn中。然后，形成其中产生压缩应力的压应力膜11以覆盖pMOS区域Rp，在nMOS区域Rn侧的压缩应力膜11的端侧表面上形成缓冲膜13，并且拉伸应力形成其中产生拉伸应力的膜12以覆盖nMOS区域Rn，压应力膜11和缓冲膜13的端部。缓冲膜13的内应力值被设定为小于压缩压应力薄膜11的应力和拉伸应力薄膜12的拉伸应力值。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2008270610A Semiconductor package 审中-公开
标题翻译：半导体封装
公开(公告)号：JP2008270610A
公开(公告)日：2008-11-06
申请号：JP2007113240
申请日：2007-04-23
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： FUJII OSAMU , IKEGAMI TOSHIHIRO
IPC分类号： H01L23/00 , H01L23/28
摘要： PROBLEM TO BE SOLVED: To achieve a semiconductor package with which a forged article can be easily identified.
SOLUTION: A semiconductor package of the present invention seals a semiconductor chip with a resin, one surface of the semiconductor package is formed from aventurine 1 with first surface coarseness, characters 12 of a product number or the like formed from aventurine 2 having second surface coarseness are provided on the aventurine 1, and the aventurine 1 and the aventurine 2 have the same reference plane.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：实现可以容易地识别锻造制品的半导体封装。解决方案：本发明的半导体封装件用树脂密封半导体芯片，半导体封装的一个表面由具有第一表面粗糙度的透明体1形成，产品编号等的字符12由具有第二表面粗糙度设置在aventurine 1上，aventurine 1和aventurine 2具有相同的参考平面。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008218574A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008218574A
公开(公告)日：2008-09-18
申请号：JP2007051889
申请日：2007-03-01
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , Toshiba Joho System Technology Kk , 東芝情報システムテクノロジー株式会社 , 東芝情報システム株式会社 , 株式会社東芝
发明人： SAWADA TATSURO , FUJII OSAMU
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a stress film capable of applying a stress efficiently to a channel region to thereby improve charge mobility.
SOLUTION: The semiconductor device includes a semiconductor substrate, a transistor which is formed on the semiconductor substrate and is isolated by an element isolating region, the stress film which is formed on the semiconductor substrate and applies a stress to the channel region of the transistor to improve charge mobility in the channel region, and a stress direction control structure which is so formed as to sandwich the channel region in the direction perpendicular to the channel direction of the stress film and increases the rate of the stress acting on the channel region by controlling the direction of a component of the stress that acts on the channel region at smaller rate.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种具有能够有效地向通道区域施加应力的应力膜的半导体器件，从而提高电荷迁移率。解决方案：半导体器件包括半导体衬底，晶体管，其形成在半导体衬底上并被元件隔离区隔离，所述应力膜形成在半导体衬底上并对应于沟道区的应力膜所述晶体管用于改善沟道区域中的电荷迁移率，以及应力方向控制结构，其形成为在垂直于应力膜的沟道方向的方向上夹持沟道区域，并增加作用在沟道上的应力的速率通过以较小的速率控制作用在通道区域上的应力的分量的方向的方向。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2010245413A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2010245413A
公开(公告)日：2010-10-28
申请号：JP2009094532
申请日：2009-04-09
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJII OSAMU
IPC分类号： H01L25/065 , H01L21/8234 , H01L25/07 , H01L25/18 , H01L27/06
CPC分类号： H01L24/73 , H01L2224/16145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that is capable of controlling power consumption while suppressing expansion of SOC chip area. SOLUTION: The semiconductor integrated circuit device includes first and second circuit blocks in which power supply wires are separated from each other, an SOC chip 12 wherein the first and second circuit blocks are formed, and SW chips 16a to 16c, in each of which a regulator circuit is formed for controlling supply of power source to the second circuit block based on the control signal from the first circuit block. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在抑制SOC芯片面积扩大的同时控制功耗的半导体集成电路器件。解决方案：半导体集成电路器件包括电源线彼此分离的第一和第二电路块，其中形成第一和第二电路块的SOC芯片12以及SW芯片16a至16c中的每一个其中形成调节器电路，用于基于来自第一电路块的控制信号控制向第二电路块的电源供应。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2010165756A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010165756A
公开(公告)日：2010-07-29
申请号：JP2009005143
申请日：2009-01-13
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社 , 株式会社東芝
发明人： KAWASHIMA DAIKI , MORIMIZU YUTAKA , FUJII OSAMU , ENDO FUMIHIKO
IPC分类号： H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for wiring which reduces offsets of a supply position, and suppresses an in-plane power supply potential difference. SOLUTION: This semiconductor device includes: a semiconductor substrate 5 having macro-cells 35; an upper high potential power supply wiring 21 which is linear on the semiconductor substrate 5, and includes trunk wiring 22a connected to a high potential pad 11 at both end parts, and nested wiring 22b crossing the trunk wiring 22a; an upper low potential power supply wiring 23 which is linear in parallel alternately on a face of the trunk wiring 22a, and includes a trunk wiring 24a connected to a low potential pad 13 at both end parts, and a nested wiring 24b crossing the trunk wiring 24a; a lower high potential power supply wiring 25 which extends linearly in parallel to the trunk wiring 22a between the semiconductor substrate 5 and the upper high potential power supply wiring 21, is connected to the macro-cells 35, and is connected to the upper high potential power supply wiring 21 by a via plug 31; and a lower low potential power supply wiring 27 which is linear in parallel alternately on a face of the lower high potential power supply wiring 25, is connected to the macro-cells 35, and is connected to the upper low potential power supply wiring 23 by the via plug 31. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供减少供给位置的偏移并且抑制面内电源电位差的布线用半导体装置。解决方案：该半导体器件包括：具有宏单元35的半导体衬底5; 在半导体基板5上呈直线状的上部高电位电源布线21，并且包括与两端部的高电位焊盘11连接的主干布线22a和与主体布线22a交叉的嵌套布线22b; 在主体布线22a的表面上交替地并行线性并且包括连接到两端部的低电位焊盘13的主干布线24a和穿过主干布线的嵌套布线24b的上部低电位电源布线23 24A; 与半导体衬底5和上部高电位电源配线21之间的主体配线22a并行延伸的下部高电位电源配线25与大电池35连接，并连接到上部高电位电源接线21由通孔塞31提供; 并且在下部高电位电源配线25的表面上交替并联成线性的低电位电源配线27连接到宏单元35，并且通过以下方式连接到上部低电位电源配线23 通过插头31.版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009054954A Semiconductor device and its authenticity discrimination method 审中-公开
标题翻译：半导体器件及其认证歧视方法
公开(公告)号：JP2009054954A
公开(公告)日：2009-03-12
申请号：JP2007222724
申请日：2007-08-29
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： FUJII OSAMU
IPC分类号： H01L23/00
摘要： PROBLEM TO BE SOLVED: To prevent the counterfeiting and imitation of a resin sealing semiconductor device while suppressing the rise of costs.
SOLUTION: A display mark 4 is provided on the resin sealing semiconductor device 30, and a recessed part 11 and a groove 12 are formed. The display mark 4 is used as a first terminal display mark and is integrally formed by a molding die. The recessed part 11 has a columnar shape, the width of the recessed part is W1(mm) and the depth of the recessed part is D1(mm). The groove 12 is provided on both end parts of the recessed part 11, the width of the groove is W2(mm), the depth of the groove is D2, and the bottom part is flat.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了防止树脂密封半导体器件的假冒和仿制，同时抑制成本的上升。解决方案：在树脂密封半导体器件30上设置有显示标记4，并且形成凹部11和凹槽12。显示标记4用作第一终端显示标记，并且通过成型模一体地形成。凹部11具有柱状，凹部的宽度为W1（mm），凹部的深度为D1（mm）。凹槽12设置在凹部11的两端部，凹槽宽度为W2（mm），凹槽的深度为D2，底部平坦。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2008072383A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008072383A
公开(公告)日：2008-03-27
申请号：JP2006248596
申请日：2006-09-13
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： IKEGAMI TOSHIHIRO , FUJII OSAMU
IPC分类号： H03L7/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of high frequency precision in clock signal and low power consumption of a system. SOLUTION: The semiconductor device comprises a control circuit 11 which controls oscillation operation of an external oscillation circuit 17 which is externally attached using an oscillation stop signal, and outputs the signal from the external oscillation circuit 17 as an external clock signal, an internal oscillation circuit 12 which generates and outputs the clock signal, and a selector 14 which selects the external clock signal or the clock signal from the internal oscillation circuit 12 based on a switching signal, and outputs it as an internal clock signal. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有时钟信号的高频精度和系统的低功耗的半导体器件。解决方案：半导体器件包括控制电路11，其控制外部振荡电路17的振荡操作，外部振荡电路17使用振荡停止信号进行外部连接，并将来自外部振荡电路17的信号作为外部时钟信号输出，内部振荡电路12，其产生并输出时钟信号;以及选择器14，其基于切换信号从内部振荡电路12选择外部时钟信号或时钟信号，并将其作为内部时钟信号输出。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2013182893A Image sensor and method of manufacturing the same 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：JP2013182893A
公开(公告)日：2013-09-12
申请号：JP2012043393
申请日：2012-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO HIROSHI , FUJII OSAMU , SHIRATO MASATAKA , MOTOMIYA YOSHINORI
IPC分类号： H01L27/146 , H04N5/369
CPC分类号： H01L27/14601 , H01L27/146 , H01L27/1463 , H01L27/14643 , H01L27/14683 , H04N5/335 , H04N5/369
摘要： PROBLEM TO BE SOLVED: To suppress variation in device characteristics caused by variation in temperature during manufacturing of an image pickup device region, thereby improving the quality.SOLUTION: There is provided an image sensor comprising: an image pickup device region 20 formed by arranging a plurality of image pickup devices 21 on a semiconductor substrate 10 and including a device separation part 23 configured to separate the image pickup devices 21; and a logic circuit region 30 formed in a region different from the image pickup device region 20 on the substrate 10 and including a plurality of gate patterns 35. A dummy device separation part 45 is formed at a constant pitch in a boundary region 40 between the image pickup device region 20 and the logic circuit region 30.
摘要翻译：要解决的问题：抑制由摄像元件区域制造过程中的温度变化引起的器件特性的变化，从而提高质量。解决方案：提供一种图像传感器，包括：图像拾取器件区域20，多个图像拾取装置21，其包括被配置为分离图像拾取装置21的装置分离部23; 以及形成在与基板10上的图像拾取器件区域20不同的区域中并且包括多个栅极图案35的逻辑电路区域30.虚设器件分离部件45以恒定的间距形成在边界区域40之间图像拾取器件区域20和逻辑电路区域30。

9. 发明专利

JP2012084796A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012084796A
公开(公告)日：2012-04-26
申请号：JP2010231633
申请日：2010-10-14
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJII OSAMU
IPC分类号： H01L21/20 , H01L21/76 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which adverse effect on, for example, the other elements on a substrate due to dislocation loops is suppressed while having a dummy pattern region that can cause the dislocation loops.SOLUTION: A semiconductor device comprises: an element isolation insulating film formed on a substrate; an element region and a dummy pattern region on the substrate that are partitioned by the element isolation insulating film; a first epitaxial crystal layer formed on the substrate in the element region; and a second epitaxial crystal layer formed on the substrate in the dummy pattern region. The first epitaxial crystal layer is composed of a crystal having a lattice constant different from a that of the crystal constituting the substrate. The second epitaxial crystal layer is composed of the same crystal as that of the first epitaxial crystal layer. The (111) plane of the substrate including any point on the interface between the second epitaxial crystal layer and the substrate is surrounded by the element isolation insulating film in a region deeper than the second epitaxial crystal layer.
摘要翻译：要解决的问题：提供一种半导体器件，其中抑制了例如位错环上的其它元件对衬底的不利影响，同时具有可能引起位错环的虚拟图案区域。解决方案：半导体器件包括：形成在衬底上的元件隔离绝缘膜; 由元件隔离绝缘膜分隔的衬底上的元件区域和虚设图案区域; 在所述元件区域中的所述基板上形成的第一外延晶体层; 以及在所述虚拟图案区域中的所述基板上形成的第二外延晶体层。第一外延晶体层由与构成基板的晶体的晶格常数不同的晶体构成。第二外延晶体层由与第一外延晶体层相同的晶体构成。包括在第二外延晶体层和衬底之间的界面上的任何点的衬底的（111）面被元件隔离绝缘膜包围在比第二外延晶体层更深的区域中。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2009099745A Production management apparatus and production management method for semiconductor device 审中-公开
标题翻译：半导体器件的生产管理设备和生产管理方法
公开(公告)号：JP2009099745A
公开(公告)日：2009-05-07
申请号：JP2007269461
申请日：2007-10-16
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJII OSAMU , YOSHIMURA HISAO , AKIYAMA TATSUO , KOMATSU SHIGERU
IPC分类号： H01L21/02 , G05B19/418
CPC分类号： Y02P90/02
摘要： PROBLEM TO BE SOLVED: To provide a production management apparatus and a production management method for a semiconductor device that can predict the yield of the semiconductor device fast during manufacturing steps and can improve the yield. SOLUTION: A manufacturing device 10 forms the semiconductor device on a semiconductor substrate. A measuring device 20 measures a featured structure of the semiconductor device formed on the semiconductor substrate by the manufacturing apparatus. An arithmetic unit 34 computes a yield value of the semiconductor device formed on the semiconductor substrate on the basis of measurement data obtained by the measuring device. A judging device 32 judges whether the manufacture of the semiconductor device is carried on or quit, or whether corrections are made from the computed yield value, and changes processing parameters of the manufacturing device when it is judged that corrections are to be made. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的生产管理装置和生产管理方法，其可以在制造步骤期间快速预测半导体器件的产量并且可以提高产量。解决方案：制造装置10在半导体衬底上形成半导体器件。测量装置20通过制造装置测量在半导体衬底上形成的半导体器件的特征结构。算术单元34基于由测量装置获得的测量数据计算形成在半导体衬底上的半导体器件的屈服值。判断装置32判断是否进行或退出半导体装置的制造，或者根据计算出的屈服值进行修正，并且在判断为要进行修正时，改变制造装置的处理参数。版权所有（C）2009，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式