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1. 发明专利

DE3874455T2 未知
公开(公告)号：DE3874455T2
公开(公告)日：1993-04-08
申请号：DE3874455
申请日：1988-07-27
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA HIDENOBU , TATSUMI YUUICHI , IWAHASHI HIROSHI , ASANO MASAMICHI , NAKAI HIROTO , IMAI MIZUHO
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34 , G11C16/06 , G11C11/34
摘要： A nonvolatile semiconductor memory device comprises a plurality of memory cell circuits each including a nonvolatile memory cell (M11) consisting of a floating gate transistor. The floating gate transistor has its source connected to a reference voltage (VS) via a conductive layer (N1) having a resistance, and a plurality of semiconductor elements are connected in series with the current path of the floating gate transistor between a power source voltage (VP) and the drain of the floating gate transistor. The effective resistances of the conductive layers between the sources of the floating gate transistors and the reference voltage (VS) are different from each other and the resistance values of the corresponding semiconductor elements are selected so as to be inversely proportional to the effective resistances between the sources of the floating gate transistors and the reference voltage (VS).

2. 发明专利

DE3884820T2 未知
公开(公告)号：DE3884820T2
公开(公告)日：1994-01-27
申请号：DE3884820
申请日：1988-07-27
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA HIDENOBU , TATSUMI YUUICHI , IWAHASHI HIROSHI , ASANO MASAMICHI , NAKAI HIROTO , IMAI MIZUHO
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34 , G11C16/06
摘要： A nonvolatile semiconductor memory device comprises a plurality of memory cell circuits each including a nonvolatile memory cell (M11) consisting of a floating gate transistor. The floating gate transistor has its source connected to a reference voltage (VS) via a conductive layer (N1) having a resistance, and a plurality of semiconductor elements are connected in series with the current path of the floating gate transistor between a power source voltage (VP) and the drain of the floating gate transistor. The effective resistances of the conductive layers between the sources of the floating gate transistors and the reference voltage (VS) are different from each other and the resistance values of the corresponding semiconductor elements are selected so as to be inversely proportional to the effective resistances between the sources of the floating gate transistors and the reference voltage (VS).

3. 发明专利

JPH02110979A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02110979A
公开(公告)日：1990-04-24
申请号：JP26316588
申请日：1988-10-19
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： INAMI MICHIHARU , ASANO MASAMICHI , MIYAGAWA TADASHI , TAURA TADAYUKI , SHOJI ATSUSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a semiconductor memory provided with an electrically erasable EEPROM cell which is small in size, capable of being highly integrated, and possessed of a gate electrode of a three-layered structure by a method wherein a source region and a drain region of cell transistors adjacent to each other in a lengthwise direction of a channel are formed in common with each other and other processes are performed. CONSTITUTION:In a nonvolatile semiconductor memory provided with a cell array composed of EEPROM cells which are arranged in a matrix and provided with gate electrodes 8, 9, and 5 of a three-layered structure, a floating gate transistor forming a channel region through the floating gate electrode 8, and a control gate transistor forming a channel region through the control gate electrode 5, a source region 3 and a drain region 4 of the memory cell are provided in parallel with each other, the source region 3 and the drain region 4 of the adjacent cells in a channel lengthwise direction of a channel region are formed in common, and the erasure gate electrode 9 and the control gate electrode 5 are provided in parallel with each other along a direction perpendicular to a broadwise direction of a channel region between the source region 3 and the drain region 4.

4. 发明专利

JPS6467797A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6467797A
公开(公告)日：1989-03-14
申请号：JP22552987
申请日：1987-09-09
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA EISHIN , IWAHASHI HIROSHI , ASANO MASAMICHI , IMAI MIZUHO , TATSUMI YUICHI
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/24
摘要： PURPOSE:To measure data read speed without writing data in a memory cell by constituting the titled device so that data '0' is read out when a dummy row line is selected during the test mode, and data '1' is read when a row line connected to a memory cell is selected. CONSTITUTION:In addition to a memory cell array 7 constituted of nonvolatile memory cells which no electrons are injected to whose floating gate and are in a state that data '1' is stored, dummy cells set in a state equivalent to a state that data '0' is stored are provided to constitute a dummy cell array 10. The array 10 is selected by the second row decoder 11 during the test mode to measure the speed of data read. As a result, the data read speed can be accurately measured without programming in a regular memory cell array.

5. 发明专利

JPS6433797A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6433797A
公开(公告)日：1989-02-03
申请号：JP18943587
申请日：1987-07-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IMAI MIZUHO , IWAHASHI HIROSHI , ASANO MASAMICHI , MINAGAWA EISHIN , TATSUMI YUICHI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent the generation of a latch-up and the enlargement of a chip by setting a boosting circuit in a device and controlling the output of a high voltage from an outside with the boosted voltage. CONSTITUTION:When a column selecting signal IN is '1' at the time of programming, a MOSTR 11 in an inverter 13 is nonconducted, a TR 12 is conducted, and an output node 15 goes to 0V. Consequently, a column selected line COLi is set to 0V through a TR 16. In such a time, current flows from a node 25 of the high voltage VP through TRs 26, 27, 22, 23 and the TR 16, and when the voltage of a node 20 is the absolute value of a threshold or more, a TR 21 is nonconducted. On the other hand, when data are read out from a memory cell, the high voltage VP of boosting circuits VH1 and VH2 and the node 25 is set to 0V, and a control signal R/W is set to '1'. In such a time, when the signal IN is '0', the TR 11 is conducted, the output of the node 15 goes to VC, and the line COLi also goes to VP through the TR 16. In such a time, the TR 22 is in a nonconductive condition, and the voltage of the line COLi is not discharged to the voltage VS.

6. 发明专利

JPS6384168A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6384168A
公开(公告)日：1988-04-14
申请号：JP23072386
申请日：1986-09-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To implement high integration density in memory cell and uniformity in electric characteristics, by forming a very thin silicon oxide film in the inside of a floating gate electrode. CONSTITUTION:N-type impurities are implanted into a substrate 10 to form an N type region 13. A silicon oxide film 16 having a thickness of 100 Angstrom is formed at a part of the region 13. A silicon oxide film 17 having a thickness of about several hundreds of Angstrom is formed in another region. A polycrystalline silicon layer is deposited on the entire surface. This layer is used as a floating gate electrode 20 of each cell, and the electrode 20 is split into parts 20A and 20B. A silicon oxide film 22 having a thickness of about several hundreds of Angstrom is formed thereon. Then, a polycrystalline silicon layer is deposited. Thereafter, the lower film 22 and the polycrystalline silicon layer beneath the film 22 are selectively etched continuously. The electrode 20 and a control electrode 23 and the gate electrodes 21 and 24 are formed in a self-aligning manner. The shape of the planar pattern of the electrode 23 is made approximately equal to that of the gate electrode 20 in the away direction of a drain and a source in each memory.

7. 发明专利

JPS6318592A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6318592A
公开(公告)日：1988-01-26
申请号：JP15974486
申请日：1986-07-09
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD , TOSHIBA MICRO CUMPUTER ENG
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO , KUMAGAI SHIGERU , SATO ISAO
IPC分类号： H01L21/8247 , G11C17/00 , H01L21/822 , H01L27/04 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To eliminate a drop in the drain voltage of a memory cell at the time of writing data, to make strong to the unevenness in a process and to write the data at high speed by using a booster circuit as a power switching circuit and applying this voltage to the buffer of a decoder. CONSTITUTION:At the time of an ordinary reading, the same voltage as VCC is impressed to the voltage of a source VPP, signals -W, HD, -HD are respectively logics '1', '0', '1', a transistor T37 is turned on and the output of a node SW1 has the same voltage as the VCC. On the other hand, at the time of writing the data, a higher voltage than the power source VCC is impressed to the power source VPP. The signals -W, HD, -HD go to the logics '0', '1', '0'. Accordingly, a signal from a ring oscillator constituted of inverters I2-I6 is applied to an inverter consisting of transistors T23-T25 and the buffer consisting of transistors T26-T28 through an inverter I7, the potential of the node SW1 is raised for every clock pulse and finally, stable at a voltage higher by the threshold voltage of the transistor T36 than the power source VPP.

8. 发明专利

JPS61255597A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61255597A
公开(公告)日：1986-11-13
申请号：JP9633585
申请日：1985-05-07
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , MINAGAWA EISHIN
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To completely enhance a reading margin without depending on a power source potential by comparing with a predetermined comparison potential to detect the data of a double gate type ROM element. CONSTITUTION:A floating gate of a transistor Mc of a potential generating circuit 30 of a comparison potential generating circuit 20 is brought to a neutral state. A potential variation owing to a variation of a power source voltage Vc of a nodal point Bc is equivalent to a cbange of a potential VBa1 owing to the variation of a voltage VCC of a nodal point Ba when ROM cells M11-Mmn of a double gate transistor in which the floating gate is brought to the neutral state. Similarly, the potential of a nodal point Bd of a comparison potential generating circuit 40 is equivalent to the variation of a potential VBa2 of the nodal point Ba when the cells M11-Mmn in which an electric charge flows in the floating gate. These nodal points Bc and Bd are connected by the transistor of a resistance component. A potential of a comparison voltage output nodal point D to a sense amplifier SA goes to an intermediate value of the potentials VBa1, VBa2. The reading margin of the ROM becomes high without depending on the power source potential.

9. 发明专利

JPH02110980A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02110980A
公开(公告)日：1990-04-24
申请号：JP26316688
申请日：1988-10-19
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： SHOJI ATSUSHI , INAMI MICHIHARU , ASANO MASAMICHI , MIYAGAWA TADASHI , TAURA TADAYUKI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a memory device which is not only excellent in integration, reliability, and a high speed operation but also electrically erasable by a method wherein an offset transistor is provided, cell transistors adjacent to each other in a widthwise direction of a channel region are isolated from each other through an element isolating region formed self-aligned with a floating gate or a control gate and other processes are performed. CONSTITUTION:A floating gate 6 is made to face toward the surface of a semiconductor substrate 1 through the intermediary of a first gate insulating film 5 and is shorter than the channel length of a channel region, an offset section is provided to one side of a part near a source/drain region 2 on the channel region where the floating gate 6 is not provided, and a control gate 8 is provided to the offset section through the intermediary of a second gate insulating film 7 facing a part of the channel region. And, cell transistors adjacent to each other in a widthwise direction of the channel region are possessed of a drain region and a source region 2 in common respectively and isolated from each other through an element isolating region 3 formed self-aligned with the floating gate 6 or the control gate 8, and the control gate 8 is made to intersect the source/drain region 2 at a right angle.

10. 发明专利

JPS6433798A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6433798A
公开(公告)日：1989-02-03
申请号：JP18943687
申请日：1987-07-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IMAI MIZUHO , IWAHASHI HIROSHI , ASANO MASAMICHI , MINAGAWA EISHIN , TATSUMI YUICHI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent the generation of a latch-up and the enlargement of a chip by discharging the output node of a CMOS circuit in a condition in which the conductive resistance of a MOS transistor for separation is high after a period to output a higher voltage than a first voltage, and thereafter, lowering the conductive resistance with a control signal. CONSTITUTION:A CMOS circuit 6 is operated by a voltage VC, and it sets an output node 1 to the voltage VC or to a voltage VS. On the other hand, the circuit impresses voltage HV 1 or HV 2, which is higher than the voltage VC, to a node 16 or 15 respectively, boosts them, and takes out the output voltage from an output line COLi. Here, the output of the CMOS circuit 6 is controlled by an inverter 11 between the voltages VC and VS, and given through an output mode 12 to a MOS transistor TR 13. A control signal S3 is applied to the TR 13, and a second voltage, which is higher than the voltage VC, discharges through the node 12 in a condition of a high conductive resistance after the output period. Thereafter, the second voltage is conducted to the MOSTR for separation by the control signal S3, and discharged. Thus, the generation of the latch-up is prevented, and the enlargement of the chip of an integrated circuit is evaded.

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