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1. 发明授权

US06877113B2 Break determining circuit for a debugging support unit in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路中的调试支持单元的断开确定电路
公开(公告)号：US06877113B2
公开(公告)日：2005-04-05
申请号：US10101777
申请日：2002-03-21
申请人： Toshiaki Saruwatari , Koutarou Tagawa
发明人： Toshiaki Saruwatari , Koutarou Tagawa
IPC分类号： G06F11/28 , G06F11/36 , G06F15/78 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A semiconductor integrated circuit including a debugging support unit and a buffer memory for temporarily storing trace data, the debugging support unit comprising a break detection member that detects a break signal externally inputted and a break determining member that determines whether the break signal requests to shift to break processing after outputting all the trace data stored in the buffer memory or the break signal requests to shift to the break processing with immediately suspending trace data outputting.
摘要翻译：一种半导体集成电路，包括用于临时存储跟踪数据的调试支持单元和缓冲存储器，所述调试支持单元包括检测外部输入的中断信号的中断检测构件和判断所述中断信号是否转移到在输出存储在缓冲存储器中的所有跟踪数据之后的中断处理或者中断信号请求以立即挂起跟踪数据输出来转移到中断处理。

2. 发明授权

US06944794B2 Microcontroller with debug support unit 失效
标题翻译：带调试支持单元的微控制器
公开(公告)号：US06944794B2
公开(公告)日：2005-09-13
申请号：US10057867
申请日：2002-01-29
申请人： Toru Okabayashi , Koutarou Tagawa
发明人： Toru Okabayashi , Koutarou Tagawa
IPC分类号： G06F11/28 , G06F11/22 , G06F11/36 , G06F15/78 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： The invention is the microcontroller, which comprises CPU, a bus controller, an instruction address bus of a first bit number and an instruction code bus of a second bit number, which connect between the CPU and bus controller, and, further, a debug support unit, which is connected to the instruction address bus and instruction code bus. This debug support unit is also connected to an external in-circuit emulator via a tool bus of a third bit number that is smaller than the first bit number and via a bus-status signal line that reports on the status of this tool bus. The debug support unit has a data output circuit, which, in response to the status information signal, when the branch information contains a branch, outputs the converted instruction address serially to the tool bus, and when the branch information contains no branch, outputs a branchless signal to the tool bus.
摘要翻译：本发明是微控制器，其包括CPU，总线控制器，第一位数的指令地址总线和连接在CPU和总线控制器之间的第二位数的指令代码总线，还有一个调试支持单元，连接到指令地址总线和指令代码总线。该调试支持单元还通过第三位数的工具总线连接到外部在线仿真器，该总线小于第一位数，并通过总线状态信号线来报告此工具总线的状态。调试支持单元具有数据输出电路，其响应于状态信息信号，当分支信息包含分支时，将转换的指令地址串行地输出到工具总线，并且当分支信息不包含分支时，输出a 无枝信号到工具总线。

3. 发明授权

US5530818A Semiconductor integrated circuit device for optionally selecting the correspondence between a chip-select signal and address space 失效
标题翻译：半导体集成电路装置，用于选择选择芯片选择信号和地址空间之间的对应关系
公开(公告)号：US5530818A
公开(公告)日：1996-06-25
申请号：US87460
申请日：1993-07-08
申请人： Koutarou Tagawa
发明人： Koutarou Tagawa
IPC分类号： G06F12/06
CPC分类号： G06F12/0653
摘要： A semiconductor integrated circuit device has a first unit for generating an address and supplying the address to an external device, a plurality of registers for storing predetermined data which designate an address space, a plurality of comparators, and a second unit. Each of the comparators is used to compare the address output from the first unit and the predetermined data stored in each of the registers. The second unit is used to merge a plurality of outputs of the comparators and to generate an enable signal to activate the external device, when at least one of the outputs of the comparators indicates coincidence between the address and the predetermined data. The semiconductor integrated circuit device makes it possible to activate the external device when at least one of the outputs of the comparators indicates coincidence between the address and the predetermined data.
摘要翻译：半导体集成电路器件具有用于产生地址并将地址提供给外部设备的第一单元，用于存储指定地址空间的预定数据的多个寄存器，多个比较器和第二单元。每个比较器用于比较来自第一单元的地址输出和存储在每个寄存器中的预定数据。第二单元用于合并比较器的多个输出，并且当比较器的输出中的至少一个指示地址和预定数据之间一致时，产生启用外部设备的使能信号。当比较器的输出中的至少一个指示地址和预定数据之间一致时，半导体集成电路器件使得可以激活外部器件。

4. 发明授权

US06594782B1 Information processing apparatus 有权
标题翻译：信息处理装置
公开(公告)号：US06594782B1
公开(公告)日：2003-07-15
申请号：US09422864
申请日：1999-10-25
申请人： Koutarou Tagawa
发明人： Koutarou Tagawa
IPC分类号： G06F1100
CPC分类号： G06F11/364
摘要： A conflict detection unit monitors an input of branch information and an input of data access information. When an output data selection unit receives a notification from the conflict detection unit that there has arisen the conflict between the input of the branch information and the input of the data access information, the output data selection unit outputs branch information, and then data access information delayed by a delay unit, thereby outputting trace data.
摘要翻译：冲突检测单元监视分支信息的输入和数据访问信息的输入。当输出数据选择单元从冲突检测单元接收到分支信息的输入和数据访问信息的输入之间产生冲突的通知时，输出数据选择单元输出分支信息，然后输出数据访问信息由延迟单元延迟，从而输出跟踪数据。

5. 发明申请

US20070069012A1 Security protected circuit 审中-公开
标题翻译：安全保护电路
公开(公告)号：US20070069012A1
公开(公告)日：2007-03-29
申请号：US11321469
申请日：2005-12-30
申请人： Koutarou Tagawa
发明人： Koutarou Tagawa
IPC分类号： G06K5/00
CPC分类号： G01R31/318558
摘要： The present invention relates to a security protected circuit in a microcomputer, and more particularly provides a security protected circuit capable of controlling whether an ICE should be used without an external terminal and for protecting security. Specifically, collation data is supplied from an ICE to a JTAG I/F and the corresponding address data of built-in memory I obtained as reference data. Then, it is determined whether both data is matched by comparing both data in a comparison circuit, and a lock mechanism is released. Even when unmatched data is equal to or less than a prescribed value, the lock mechanism is released. Thus, a lock release device which protects security can be provided without providing a special terminal for lock release.
摘要翻译：本发明涉及一种微型计算机中的安全保护电路，更具体地说，提供一种安全保护电路，其能够控制是否在没有外部终端的情况下使用ICE并且用于保护安全性。具体地，核对数据从ICE提供给JTAG I / F以及作为参考数据获得的内置存储器I的相应地址数据。然后，通过比较比较电路中的两个数据来确定两个数据是否匹配，并且释放锁定机制。即使不匹配的数据等于或小于规定值，也释放锁定机构。因此，可以提供保护安全性的锁定释放装置，而不需要提供用于锁定释放的特殊终端。

6. 发明申请

US20060075310A1 Microcomputer and trace control method capable of tracing desired task 审中-公开
标题翻译：微电脑跟踪控制方法能够跟踪所需任务
公开(公告)号：US20060075310A1
公开(公告)日：2006-04-06
申请号：US11023646
申请日：2004-12-29
申请人： Koutarou Tagawa
发明人： Koutarou Tagawa
IPC分类号： G06F11/00
CPC分类号： G06F11/364
摘要： A microcomputer includes a bus, a CPU coupled to the bus, a trace data generating circuit coupled to the bus to output trace data of a process executed by the CPU at an output node, a memory coupled to the output node of the trace data generating circuit to store the trace data, a first register coupled to the bus to store a task number indicative of a task being executed by the CPU, and a control unit coupled to the first register to control on/off of outputting of the trace data from the trace data generating circuit in response to the task number.
摘要翻译：微型计算机包括总线，耦合到总线的CPU，耦合到总线的跟踪数据产生电路，以输出由CPU在输出节点执行的处理的跟踪数据;存储器，耦合到产生跟踪数据的输出节点用于存储跟踪数据的电路，耦合到总线以存储指示由CPU执行的任务的任务号码的第一寄存器以及耦合到第一寄存器的控制单元，以控制从/ 轨迹数据产生电路响应任务号码。

7. 发明授权

US06922794B2 Microcomputer with debug supporting function 有权
标题翻译：微电脑具有调试支持功能
公开(公告)号：US06922794B2
公开(公告)日：2005-07-26
申请号：US09960519
申请日：2001-09-24
申请人： Koutarou Tagawa , Kouj Arai
发明人： Koutarou Tagawa , Kouj Arai
IPC分类号： G06F11/22 , G06F11/36 , G06F15/78 , G06F11/00
CPC分类号： G06F11/3648
摘要： In the microcomputer, the debug target circuit and the debugging circuit with an interface module to the in-circuit emulator are independently supplied with drive powers. Drive power is supplied to the debug target circuit and the debugging circuit, and various debug information is set by the in-circuit emulator. Thereafter, only supply of drive power to the debug target circuit is stopped. While the various debug information is held at the debugging circuit, supply of drive power to the debug target circuit is restarted. The debugging just after power throw-in is performed based on the debug information held in the debugging circuit.
摘要翻译：在微型计算机中，调试目标电路和具有到在线仿真器的接口模块的调试电路独立提供驱动功率。驱动电源提供给调试目标电路和调试电路，各种调试信息由在线仿真器设置。此后，仅停止向调试目标电路提供驱动电力。在调试电路中保持各种调试信息的同时，再次向调试对象电路供给驱动电力。基于调试电路中保存的调试信息执行掉电后的调试。

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