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1. 发明授权

US06727552B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06727552B2
公开(公告)日：2004-04-27
申请号：US10062462
申请日：2002-02-05
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L2701
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

2. 发明授权

US06649976B2 Semiconductor device having metal silicide film and manufacturing method thereof 失效
公开(公告)号：US06649976B2
公开(公告)日：2003-11-18
申请号：US09982777
申请日：2001-10-22
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L2976
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

3. 发明授权

US6051494A Semiconductor device having metal silicide film 失效
标题翻译：具有金属硅化物膜的半导体器件
公开(公告)号：US6051494A
公开(公告)日：2000-04-18
申请号：US855259
申请日：1997-05-13
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/78 , H01L29/786 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L21/26586 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
摘要翻译：可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。因此，在源极区域中，可以形成更厚的硅化钛膜。

4. 发明授权

US06198134B1 Semiconductor device having a common substrate bias 失效
标题翻译：具有公共衬底偏置的半导体器件
公开(公告)号：US06198134B1
公开(公告)日：2001-03-06
申请号：US09056616
申请日：1998-04-08
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L2701
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

5. 发明授权

US5937284A Method of making a semiconductor device having an SOI structure 失效
标题翻译：制造具有SOI结构的半导体器件的方法
公开(公告)号：US5937284A
公开(公告)日：1999-08-10
申请号：US979621
申请日：1997-11-28
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Tadashi Nishimura
IPC分类号： H01L27/12 , H01L21/00 , H01L21/425 , H01L21/76
CPC分类号： H01L27/1203
摘要： Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.
摘要翻译：防止有源层边缘中的寄生晶体管的产生。在绝缘膜（20）上的半导体层（21）的NMOS区域中，使用氮化膜（23）和抗蚀剂（253a）作为掩模，通过旋转倾斜注入注入硼离子。在通过LOCOS方法分离元件的区域附近，即仅在作为NMOS晶体管的有源层的半导体层（21）的边缘区域中，硼离子注入约3×10 13 / cm 2。在LOCOS氧化之后，杂质浓度提高到这样的水平，因为硼离子可能不被吸入氧化膜中。

6. 发明授权

US5801080A Method of manufacturing semiconductor substrate having total and partial dielectric isolation 失效
标题翻译：制造具有全部和部分电介质隔离的半导体衬底的方法
公开(公告)号：US5801080A
公开(公告)日：1998-09-01
申请号：US837959
申请日：1997-04-14
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/84 , H01L23/482 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

7. 发明授权

US5652454A Semiconductor device on an SOI substrate 失效
标题翻译： SOI衬底上的半导体器件
公开(公告)号：US5652454A
公开(公告)日：1997-07-29
申请号：US675510
申请日：1996-07-03
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/84 , H01L23/482 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/01 , H01L23/58 , H01L29/00
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

8. 发明授权

US5381235A Three-dimensional shape measuring device and three-dimensional shape measuring sensor 失效
标题翻译：三维形状测量装置和三维形状测量传感器
公开(公告)号：US5381235A
公开(公告)日：1995-01-10
申请号：US990460
申请日：1992-12-15
申请人： Yasuo Inoue , Tadashi Nishimura , Takashi Ipposhi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Takashi Ipposhi , Toshiaki Iwamatsu
IPC分类号： G01B11/24 , G01B11/02 , G01B11/25 , G01C3/06 , H01L27/14
CPC分类号： G01B11/024 , G01B11/2518
摘要： The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device. The three-dimensional shape measuring device comprises a light source for scanning plane light over the surface of an object, an image sensor opposed to the object and provided with a plurality of pixels, an optical system for forming an image of a bright line appearing on the surface of the object due to plane light on the image sensor, a plurality of capacitors installed in association with pixels of the image sensor, a charger for storing given charges in a plurality of capacitors before plane light scanning starts, a plurality of dischargers lying in association with capacitors and gradually discharging the capacitors for pixels corresponding to a bright line image from when plane light scanning starts until the bright line image passes through the pixels, and an arithmetic logic means for computing charges remaining in the plurality of capacitors after plane light scanning is completed and thus providing a three-dimensional shape of an object. Thereby, a three-dimensional shape of an object can be measured at a high speed with high precision.
摘要翻译：本发明提供了三维形状测量装置和用于三维形状测量装置的传感器。三维形状测量装置包括：用于扫描物体表面上的平面光的光源，与该物体相对并设置有多个像素的图像传感器，用于形成亮线的图像的光学系统，由于图像传感器上的平面光，物体的表面，与图像传感器的像素相关联地安装的多个电容器，用于在平面光扫描开始之前在多个电容器中存储给定电荷的充电器，多个放电器位于与平面光扫描开始直到亮线图像通过像素的与亮线图像相对应的像素的电容器逐渐放电;以及算术逻辑装置，用于计算平面光后的多个电容器中剩余的电荷扫描完成，从而提供对象的三维形状。由此，可以高精度地测量物体的三维形状。

9. 发明授权

US5659194A Semiconductor device having metal silicide film 失效
标题翻译：具有金属硅化物膜的半导体器件
公开(公告)号：US5659194A
公开(公告)日：1997-08-19
申请号：US614256
申请日：1996-03-12
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/26506 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L21/26586 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
摘要翻译：可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。因此，在源极区域中，可以形成更厚的硅化钛膜。

10. 发明授权

US5440161A Semiconductor device having an SOI structure and a manufacturing method thereof 失效
标题翻译：具有SOI结构的半导体器件及其制造方法
公开(公告)号：US5440161A
公开(公告)日：1995-08-08
申请号：US273175
申请日：1994-07-26
申请人： Toshiaki Iwamatsu , Yasuo Yamaguchi , Yasuo Inoue , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Yamaguchi , Yasuo Inoue , Tadashi Nishimura
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/108 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/786 , H01L27/01 , H01L21/265
CPC分类号： H01L29/402 , H01L21/84 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： A buried oxide film 4 is formed on a main surface of a silicon substrate 1. An SOI layer 5 is formed on buried oxide film 4. Channel stop regions 22a and 22b respectively connected to channel regions of an nMOS 2 and a pMOS 3 are formed in an element isolation region of SOI layer 5. nMOS 2 and pMOS 3 are formed in an element formation region of SOI layer. A concentration of a p type impurity or an n type impurity included in channel stop regions 22a and 22b is higher than a concentration of the p type impurity or the n type impurity included in the channel region of nMOS 2 or the channel region of pMOS 3. An FS gate 16 is formed on channel stop regions 22a and 22b with an FS gate oxide film 15 interposed therebetween. Therefore, a semiconductor device having an SOI structure which is capable of suppressing a parasitic bipolar operation by drawing out efficiently excessive carriers stored in the channel region of transistor can be obtained.
摘要翻译：在硅衬底1的主表面上形成掩埋氧化膜4.在掩埋氧化物膜4上形成SOI层5.形成分别连接到nMOS 2和pMOS 3的沟道区的沟道停止区22a和22b 在SOI层5的元件隔离区域中，在SOI层的元件形成区域中形成nMOS 2和pMOS 3。包含在通道停止区域22a和22b中的ap型杂质或n型杂质的浓度高于包含在nMOS 2的沟道区域或pMOS 3的沟道区域中的p型杂质或n型杂质的浓度。 FS沟道栅极16形成在通道阻挡区域22a和22b上，其中FS栅氧化膜15插入其间。因此，可以获得具有SOI结构的半导体器件，该半导体器件能够通过有效地抽出存储在晶体管的沟道区域中的过多的载流子来抑制寄生双极性操作。

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