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1. 发明授权

US07595627B1 Voltage reference circuit with complementary PTAT voltage generators and method 有权
标题翻译：具有互补PTAT电压发生器和方法的电压参考电路
公开(公告)号：US07595627B1
公开(公告)日：2009-09-29
申请号：US11900993
申请日：2007-09-14
申请人： Torsten Mahnke , Stephan Drebinger , Michael Brauer
发明人： Torsten Mahnke , Stephan Drebinger , Michael Brauer
IPC分类号： G05F3/16
CPC分类号： G05F3/16
摘要： A voltage reference circuit is provided. The voltage reference circuit includes a first PTAT voltage generator and an amplifier. The first PTAT voltage generator is operable to generate a first PTAT voltage. The amplifier, which is coupled to the first PTAT voltage generator, comprises a second PTAT voltage generator that is complementary to the first PTAT voltage generator. The second PTAT voltage generator is operable to generate a second PTAT voltage. The amplifier is operable to generate a reference voltage based on the first PTAT voltage and the second PTAT voltage.
摘要翻译：提供电压参考电路。电压参考电路包括第一PTAT电压发生器和放大器。第一PTAT电压发生器可操作以产生第一PTAT电压。耦合到第一PTAT电压发生器的放大器包括与第一PTAT电压发生器互补的第二PTAT电压发生器。第二PTAT电压发生器可操作以产生第二PTAT电压。放大器可操作以基于第一PTAT电压和第二PTAT电压产生参考电压。

2. 发明授权

US08564359B2 Method and system for controlling HS-NMOS power switches with slew-rate limitation 有权
标题翻译：用于控制具有压摆率限制的HS-NMOS功率开关的方法和系统
公开(公告)号：US08564359B2
公开(公告)日：2013-10-22
申请号：US12807769
申请日：2010-09-14
申请人： Michael Brauer , Stephan Drebinger
发明人： Michael Brauer , Stephan Drebinger
IPC分类号： H03K17/687
CPC分类号： H03K5/01 , H03K17/166 , H03K2017/6875 , H03K2217/0054
摘要： A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.
摘要翻译：公开了一种用于限制一个或多个高侧（HS）NMOS功率开关的输出电压的转换速率的方法和系统。描述配置成控制第一NMOS开关的电路装置。该装置包括电压供应装置，被配置为向第一NMOS开关的栅极端提供栅极电压; 配置为提供电流的电流供应装置; 第一控制级，被配置为提供和/或去除第一NMOS开关的栅极端子和电压供应装置之间的连接，从而分别将第一NMOS开关切换到导通状态和/或截止状态; 以及第一NMOS开关的输出端子和被配置为控制第一输出端子处的电压的转换速率的电流供应装置之间的第一反馈控制链路。

3. 发明申请

US20120056655A1 Method and system for controlling HS-NMOS power switches with slew-rate limitation 有权
标题翻译：用于控制具有压摆率限制的HS-NMOS功率开关的方法和系统
公开(公告)号：US20120056655A1
公开(公告)日：2012-03-08
申请号：US12807769
申请日：2010-09-14
申请人： Michael Brauer , Stephan Drebinger
发明人： Michael Brauer , Stephan Drebinger
IPC分类号： H03K5/12
CPC分类号： H03K5/01 , H03K17/166 , H03K2017/6875 , H03K2217/0054
摘要： A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.
摘要翻译：公开了一种用于限制一个或多个高侧（HS）NMOS功率开关的输出电压的转换速率的方法和系统。描述配置成控制第一NMOS开关的电路装置。该装置包括电压供应装置，被配置为向第一NMOS开关的栅极端提供栅极电压; 配置为提供电流的电流供应装置; 第一控制级，被配置为提供和/或去除第一NMOS开关的栅极端子和电压供应装置之间的连接，从而分别将第一NMOS开关切换到导通状态和/或截止状态; 以及第一NMOS开关的输出端子和被配置为控制第一输出端子处的电压的转换速率的电流供应装置之间的第一反馈控制链路。

4. 发明授权

US09086714B2 High-speed LDO driver circuit using adaptive impedance control 有权
标题翻译：高速LDO驱动电路采用自适应阻抗控制
公开(公告)号：US09086714B2
公开(公告)日：2015-07-21
申请号：US13530305
申请日：2012-06-22
申请人： Liu Liu , Stephan Drebinger
发明人： Liu Liu , Stephan Drebinger
IPC分类号： G05F1/565 , G05F1/575 , G05F3/30
CPC分类号： G05F1/575 , G05F3/30
摘要： The present document relates to linear regulators or linear voltage regulators configured to provide a constant output voltage. In particular, the present document relates to driver circuits of low-dropout (LDO) regulators. A driver circuit (300) for driving a pass device (201) of a linear regulator (120) is described. The driver circuit (300) comprises a driver stage (110) adapted to regulate a driver gate (220) for connecting to the gate of the pass device (201); wherein the driver stage (110) comprises a transistor diode (210) having the driver gate (220); and a feedback transistor (305) having a source and a drain coupled to a source and drain of the transistor diode (210); wherein a feedback voltage at the gate of the feedback transistor (305) is regulated based on the output current of the pass device (201).
摘要翻译：本文件涉及配置成提供恒定输出电压的线性稳压器或线性稳压器。特别地，本文件涉及低压差（LDO）调节器的驱动器电路。描述了用于驱动线性调节器（120）的通过装置（201）的驱动器电路（300）。驱动器电路（300）包括适于调节用于连接到通过装置（201）的门的驱动器门（220）的驱动器级（110）。其中所述驱动器级（110）包括具有所述驱动器门（220）的晶体管二极管（210）。以及反馈晶体管（305），其具有耦合到晶体管二极管（210）的源极和漏极的源极和漏极; 其中，基于所述通过装置（201）的输出电流来调节所述反馈晶体管（305）的栅极处的反馈电压。

5. 发明授权

US07200042B2 Method and circuit arrangement for reading from a flash/EEPROM memory cell 有权
标题翻译：用于从闪存/ EEPROM存储单元读取的方法和电路装置
公开(公告)号：US07200042B2
公开(公告)日：2007-04-03
申请号：US11230301
申请日：2005-09-19
申请人： Stephan Drebinger
发明人： Stephan Drebinger
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063
摘要： The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with a reference memory cell that simulates the memory cell and has a reference memory transistor simulating the memory transistor. According to the invention, it is provided that firstly, in a first step, the reference memory transistor is brought to the normally on state provided that the reference memory transistor is not already in the normally on state. In a second step, it is provided that a predetermined reference current is fed into the at least one read-out path simulation. Unlike in the prior art, said reference current is not derived from a reference voltage. In a third step, provision is made for generating, with the aid of the predetermined reference current, a reference voltage that is dependent on the channel resistance of the reference memory transistor. In a fourth step, the reference voltage generated is applied to the gate of the memory transistor and the gate of the reference memory transistor. In a fifth step, the read current flowing through the memory transistor is compared with the predetermined reference current flowing through the reference memory transistor.
摘要翻译：本发明基于读出闪存/ EEPROM存储单元的内容的方法，其中通过具有存储晶体管的存储单元经由读出路径流动的读取电流与至少流过的参考电流进行比较一个读出路径模拟与参考存储单元模拟存储单元，并具有模拟存储晶体管的参考存储晶体管。根据本发明，首先，在第一步骤中，如果参考存储晶体管尚未处于正常导通状态，则参考存储晶体管处于正常导通状态。在第二步骤中，提供了将预定参考电流馈送到所述至少一个读出路径模拟中。与现有技术不同，所述参考电流不是从参考电压得出的。在第三步骤中，提供了借助于预定参考电流产生取决于参考存储晶体管的沟道电阻的参考电压。在第四步骤中，所产生的参考电压被施加到存储晶体管的栅极和参考存储晶体管的栅极。在第五步骤中，将流过存储晶体管的读取电流与流过参考存储晶体管的预定参考电流进行比较。

6. 发明授权

US08513929B2 Method for providing and operating an LDO 有权
标题翻译：提供和操作LDO的方法
公开(公告)号：US08513929B2
公开(公告)日：2013-08-20
申请号：US12927491
申请日：2010-11-16
申请人： Stephan Drebinger
发明人： Stephan Drebinger
IPC分类号： G05F1/00
CPC分类号： G05F1/575
摘要： The LDO has at least three stages supplied by a supply voltage. A first stage has a differential amplifier and a folded cascode device with a regulated current mirror. The LDO has two nodes that are configured to couple the differential amplifier and the regulated current mirror and to receive a differential signal, respectively. The regulated current mirror is configured to convert and amplify the differential signals to a single ended signal. Said LDO has a first capacitor configured for frequency compensation, said first capacitor coupled between said first stage and a second stage. The LDO has a second capacitor for balancing capacitive loading of a first cascode circuit, said second capacitor coupled between said first stage and said supply voltage. Said first cascode circuit is configured to suppress different voltages between input and output of the capacitors caused of a modulation of said supply voltage. The LDO has a second cascode circuit configured to suppress supply modulations of the differential amplifier.
摘要翻译： LDO至少由供电电压提供三级。第一级具有差分放大器和具有调节电流镜的折叠共源共栅器件。 LDO有两个节点，分别配置成耦合差分放大器和调节电流镜，并分别接收差分信号。调节电流镜被配置为将差分信号转换并放大到单端信号。所述LDO具有配置用于频率补偿的第一电容器，所述第一电容器耦合在所述第一级和第二级之间。 LDO具有用于平衡第一共源共栅电路的电容负载的第二电容器，所述第二电容器耦合在所述第一级与所述电源电压之间。所述第一级联电路被配置为抑制由所述电源电压的调制引起的电容器的输入和输出之间的不同电压。 LDO具有被配置为抑制差分放大器的电源调制的第二级联电路。

7. 发明申请

US20130147447A1 High-Speed LDO Driver Circuit using Adaptive Impedance Control 有权
标题翻译：使用自适应阻抗控制的高速LDO驱动电路
公开(公告)号：US20130147447A1
公开(公告)日：2013-06-13
申请号：US13530305
申请日：2012-06-22
申请人： Liu Liu , Stephan Drebinger
发明人： Liu Liu , Stephan Drebinger
IPC分类号： G05F1/10 , H03K3/00
CPC分类号： G05F1/575 , G05F3/30
摘要： The present document relates to linear regulators or linear voltage regulators configured to provide a constant output voltage. In particular, the present document relates to driver circuits of low-dropout (LDO) regulators. A driver circuit (300) for driving a pass device (201) of a linear regulator (120) is described. The driver circuit (300) comprises a driver stage (110) adapted to regulate a driver gate (220) for connecting to the gate of the pass device (201); wherein the driver stage (110) comprises a transistor diode (210) having the driver gate (220); and a feedback transistor (305) having a source and a drain coupled to a source and drain of the transistor diode (210); wherein a feedback voltage at the gate of the feedback transistor (305) is regulated based on the output current of the pass device (201).
摘要翻译：本文件涉及配置成提供恒定输出电压的线性稳压器或线性稳压器。特别地，本文件涉及低压差（LDO）调节器的驱动器电路。描述了用于驱动线性调节器（120）的通过装置（201）的驱动器电路（300）。驱动器电路（300）包括适于调节用于连接到通过装置（201）的门的驱动器门（220）的驱动器级（110）。其中所述驱动器级（110）包括具有所述驱动器门（220）的晶体管二极管（210）。以及反馈晶体管（305），其具有耦合到晶体管二极管（210）的源极和漏极的源极和漏极; 其中，基于所述通过装置（201）的输出电流来调节所述反馈晶体管（305）的栅极处的反馈电压。

8. 发明申请

US20120280667A1 Flexible load current dependent feedback compensation for linear regulators utilizing ultra-low bypass capacitances 审中-公开
标题翻译：适用于使用超低旁路电容的线性稳压器的灵活负载电流相关反馈补偿
公开(公告)号：US20120280667A1
公开(公告)日：2012-11-08
申请号：US13136257
申请日：2011-07-27
申请人： Stephan Drebinger , Marcus Weis , Liu Liu
发明人： Stephan Drebinger , Marcus Weis , Liu Liu
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： The present document relates to low-dropout (LDO) regulators having low output capacitance. The regulator comprises a differential amplification stage configured to amplify a differential voltage between a reference voltage and a measure of the output voltage, thereby yielding a drive current at an output of the amplification stage; a subsequent output amplification stage configured to provide the regulated output voltage and a output current at an output of the output amplification stage, based on a drive voltage at an input of the output amplification stage; and a first output current feedback loop configured to sense the output current; and feed back a first coupling current derived from the sensed output current to a first intermediate point between the output of the differential amplification stage and the input of the output amplification stage; wherein the drive voltage is dependent on the drive current and the first coupling current.
摘要翻译：本文件涉及具有低输出电容的低压差（LDO）调节器。调节器包括差分放大级，其被配置为放大参考电压和输出电压的测量之间的差分电压，从而在放大级的输出端产生驱动电流; 随后的输出放大级，被配置为基于输出放大级的输入处的驱动电压来提供输出放大级的输出处的调节输出电压和输出电流; 以及被配置为感测所述输出电流的第一输出电流反馈回路; 并将从所感测的输出电流导出的第一耦合电流反馈到差分放大级的输出与输出放大级的输入之间的第一中间点; 其中驱动电压取决于驱动电流和第一耦合电流。

9. 发明申请

US20110121800A1 Method for providing and operating an LDO 有权
标题翻译：提供和操作LDO的方法
公开(公告)号：US20110121800A1
公开(公告)日：2011-05-26
申请号：US12927491
申请日：2010-11-16
申请人： Stephan Drebinger
发明人： Stephan Drebinger
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： The LDO has at least three stages supplied by a supply voltage. A first stage has a differential amplifier and a folded cascode device with a regulated current mirror. The LDO has two nodes that are configured to couple the differential amplifier and the regulated current mirror and to receive a differential signal, respectively. The regulated current mirror is configured to convert and amplify the differential signals to a single ended signal. Said LDO has a first capacitor configured for frequency compensation, said first capacitor coupled between said first stage and a second stage. The LDO has a second capacitor for balancing capacitive loading of a first cascode circuit, said second capacitor coupled between said first stage and said supply voltage. Said first cascode circuit is configured to suppress different voltages between input and output of the capacitors caused of a modulation of said supply voltage. The LDO has a second cascode circuit configured to suppress supply modulations of the differential amplifier.
摘要翻译： LDO至少由供电电压提供三级。第一级具有差分放大器和具有调节电流镜的折叠共源共栅器件。 LDO有两个节点，分别配置成耦合差分放大器和调节电流镜，并分别接收差分信号。调节电流镜被配置为将差分信号转换并放大到单端信号。所述LDO具有配置用于频率补偿的第一电容器，所述第一电容器耦合在所述第一级和第二级之间。 LDO具有用于平衡第一共源共栅电路的电容负载的第二电容器，所述第二电容器耦合在所述第一级与所述电源电压之间。所述第一级联电路被配置为抑制由所述电源电压的调制引起的电容器的输入和输出之间的不同电压。 LDO具有被配置为抑制差分放大器的电源调制的第二级联电路。

10. 发明授权

US07629785B1 Circuit and method supporting a one-volt bandgap architecture 有权
标题翻译：支持一伏带隙结构的电路和方法
公开(公告)号：US07629785B1
公开(公告)日：2009-12-08
申请号：US11805334
申请日：2007-05-23
申请人： Stephan Drebinger
发明人： Stephan Drebinger
IPC分类号： G05F3/20 , G05F3/28
CPC分类号： G05F3/30 , Y10S323/907
摘要： A system includes a transistor coupled to a voltage rail, a first resistor coupled in series with the transistor, and a second resistor coupled in series with the first resistor. The system also includes a bandgap reference circuit operable to generate a bandgap reference voltage of less than 1.2 volts (such as one volt) between the first and second resistors. The bandgap reference circuit includes a diode configured to generate a complementary-to-absolute-temperature (CTAT) voltage and a third resistor configured to generate a first proportional-to-absolute-temperature (PTAT) voltage using a first current. The bandgap reference circuit also includes a current source configured to sink a CTAT current from the first current to generate a second current and a fourth resistor configured to generate a second PTAT voltage using the second current. A sum of the CTAT voltage, the first PTAT voltage, and the second PTAT voltage is less than 1.2 volts.
摘要翻译：系统包括耦合到电压轨的晶体管，与晶体管串联耦合的第一电阻器，以及与第一电阻器串联耦合的第二电阻器。该系统还包括带隙参考电路，其可操作以在第一和第二电阻器之间产生小于1.2伏（例如一伏特）的带隙基准电压。带隙参考电路包括被配置为产生互补绝对温度（CTAT）电压的二极管和被配置为使用第一电流产生第一比例绝对温度（PTAT）电压的第三电阻器。带隙参考电路还包括被配置为从第一电流吸收CTAT电流以产生第二电流的电流源和被配置为使用第二电流产生第二PTAT电压的第四电阻。 CTAT电压，第一PTAT电压和第二PTAT电压之和小于1.2伏特。

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