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1. 发明授权

US5963736A Software reconfigurable target I/O in a circuit emulation system 失效
标题翻译：电路仿真系统中的软件可重构目标I / O
公开(公告)号：US5963736A
公开(公告)日：1999-10-05
申请号：US805852
申请日：1997-03-03
申请人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Curt Blanding
发明人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Curt Blanding
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F11/261
摘要： A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.
摘要翻译：时间分片的基于硬件的仿真器，其包括以下中的至少一个：可编程I / O分配; 可编程电平的直流电压; 以引脚为基础在仿真器中编程上拉或下拉电阻; 可编程强制和/或禁用每个引脚上仿真器的值输出; 可编程时钟; 和可编程采样模式。仿真器通过Pod系统接口（PSI），专门设计的电缆和Pod用户界面（PUI）连接到目标系统。对于从仿真器传输到目标系统的数据，每个PSI从仿真器接收高达128位的数据。然而，电缆只有32位宽。因此，仿真器将通过电缆发送的数据进行多路复用，根据快速时钟信号向PC发送8位交错的32位组。每个PUI从PSI接收32位的组，并根据来自仿真器的控制信号将它们发送到目标系统。对于从目标系统传输到仿真器的数据，每个PUI从目标系统接收高达128位的数据。每个PUI根据快速时钟信号发送四组32位。每个PSI接收32位组并将它们保存在一个内部寄存器中，在仿真器的控制下将接收到的位发送到仿真器。

2. 发明授权

US6141636A Logic analysis subsystem in a time-sliced emulator 失效
标题翻译：时分片仿真器中的逻辑分析子系统
公开(公告)号：US6141636A
公开(公告)日：2000-10-31
申请号：US831501
申请日：1997-03-31
申请人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Bernard Y. Chan , Michael C. Tsou
发明人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Bernard Y. Chan , Michael C. Tsou
IPC分类号： G06F17/50 , G06F11/25 , G06F11/26 , G06F11/34 , G06F9/455
CPC分类号： G06F11/261 , G06F11/25 , G06F11/3466
摘要： A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.
摘要翻译：时间分片仿真器中的逻辑分析子系统。逻辑分析子系统“重建”先前由编译器减少的信号，并允许用户使用仿真电路的这些和其他信号来设置断点和触发。本发明包括“逻辑分析子系统编译器”和“逻辑分析子系统硬件”。逻辑分析子系统编译器是常规仿真器编译器的子部分，也可以是独立编译器。它编译要仿真的设计，并为逻辑分析子系统硬件生成控制指令。逻辑分析子系统硬件被并入到时间分割的仿真器中，以在仿真期间接收由仿真器产生的信号。当逻辑分析子系统运行时，控制指令使逻辑分析子系统重建从仿真器接收的先前减小的信号。这些信号（以及从仿真器接收到的信号）可以由用户用于在逻辑分析子系统中设置断点和触发器。

3. 发明授权

US5369593A System for and method of connecting a hardware modeling element to a hardware modeling system 失效
标题翻译：将硬件建模元件连接到硬件建模系统的系统和方法
公开(公告)号：US5369593A
公开(公告)日：1994-11-29
申请号：US780529
申请日：1991-10-18
申请人： Mark S. Papamarcos , Andrew J. Read , Wayne P. Heideman , Robert K. Mardjuki , Robert K. Couch , Peter R. Jaeger , William F. Kappauf , Melvin Rudin , Norman F. Kelly , Lawrence C. Widdoes, Jr.
发明人： Mark S. Papamarcos , Andrew J. Read , Wayne P. Heideman , Robert K. Mardjuki , Robert K. Couch , Peter R. Jaeger , William F. Kappauf , Melvin Rudin , Norman F. Kelly , Lawrence C. Widdoes, Jr.
IPC分类号： G01R31/3183 , G06F17/50 , H01R29/00 , H01R11/01
CPC分类号： G01R31/318357 , H01R29/00 , Y10S439/955
摘要： An improved system for and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.
摘要翻译：一种用于将硬件建模元件连接到硬件建模系统的引脚电子电路的改进的系统和方法，所述改进的系统具有允许其连接到被供电的硬件建模系统的电路和结构，以指示到改进的系统连接到引脚电子电路，用于将由改进的系统支持的硬件建模元件识别到硬件建模系统的电路，用于在硬件建模元件被初始化时向硬件建模系统指示的电路，以评估可以开始通过硬件建模系统生成用于为硬件建模元件供电的可选电源电压的电路，以及将允许一系列硬件建模元件连接到同一连接器而不需要改变的硬件建模元件连接器连接器。

4. 发明授权

US5353243A Hardware modeling system and method of use 失效
标题翻译：硬件建模系统及使用方法
公开(公告)号：US5353243A
公开(公告)日：1994-10-04
申请号：US939393
申请日：1992-08-31
申请人： Andrew J. Read , Mark S. Papamarcos , Wayne P. Heideman , Robert K. Mardjuki , Robert K. Couch , Peter R. Jaeger , William F. Kappauf , Lawrence C. Widdoes, Jr. , Louis K. Scheffer
发明人： Andrew J. Read , Mark S. Papamarcos , Wayne P. Heideman , Robert K. Mardjuki , Robert K. Couch , Peter R. Jaeger , William F. Kappauf , Lawrence C. Widdoes, Jr. , Louis K. Scheffer
IPC分类号： G01R31/319 , G06F17/50 , G06F15/20
CPC分类号： G06F17/5022 , G01R31/31919 , G01R31/31928
摘要： An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.
摘要翻译：改进的硬件建模系统优选地被实现为用于与用于设计数字电子系统的一个或多个主机的网络连接的独立系统，所述硬件建模系统具有用于在硬件建模系统以及主计算机，用于控制硬件建模系统的操作的中央处理单元，用于产生用于硬件建模系统的操作中使用的定时信号的中央定时单元，包括精密时钟的产生，数据格式化选通和采样选通，用于以一种操作模式从中央处理单元传输读/写请求的内部模式总线，以及用于在第二操作模式下刺激硬件建模元件的模式序列，用于控制模式序列的呈现和传递的模式控制器模式总线，连接到模式的模式存储器用于存储刺激图案序列的引脚电子电路，其用于将模式总线上的图案序列驱动到硬件建模元件，然后感测硬件建模元件引脚的五个状态值，以及用于固定硬件建模元件到引脚电子电路，适配器支持实时插入到电源硬件建模系统中。

5. 发明授权

US5625580A Hardware modeling system and method of use 失效
标题翻译：硬件建模系统及使用方法
公开(公告)号：US5625580A
公开(公告)日：1997-04-29
申请号：US313529
申请日：1994-09-26
申请人： Andrew J. Read , Mark S. Papamarcos , Wayne P. Heideman , Robert K. Mardjuki , Robert K. Couch , Peter R. Jaeger , William F. Kappauf , Lawrence C. Widdoes, Jr. , Louis K. Scheffer
发明人： Andrew J. Read , Mark S. Papamarcos , Wayne P. Heideman , Robert K. Mardjuki , Robert K. Couch , Peter R. Jaeger , William F. Kappauf , Lawrence C. Widdoes, Jr. , Louis K. Scheffer
IPC分类号： G01R31/319 , G06F17/50 , G06F17/00
CPC分类号： G06F17/5022 , G01R31/31919 , G01R31/31928
摘要： An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.
摘要翻译：改进的硬件建模系统优选地被实现为用于与用于设计数字电子系统的一个或多个主机的网络连接的独立系统，所述硬件建模系统具有用于在硬件建模系统以及主计算机，用于控制硬件建模系统的操作的中央处理单元，用于产生用于硬件建模系统的操作中使用的定时信号的中央定时单元，包括精密时钟的产生，数据格式化选通和采样选通，用于以一种操作模式从中央处理单元传输读/写请求的内部模式总线，以及用于在第二操作模式下刺激硬件建模元件的模式序列，用于控制模式序列的呈现和传递的模式控制器模式总线，连接到模式的模式存储器用于存储刺激图案序列的引脚电子电路，其用于将模式总线上的图案序列驱动到硬件建模元件，然后感测硬件建模元件引脚的五个状态值，以及用于固定硬件建模元件到引脚电子电路，适配器支持实时插入到电源硬件建模系统中。

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