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1. 发明授权

US6141636A Logic analysis subsystem in a time-sliced emulator 失效
标题翻译：时分片仿真器中的逻辑分析子系统
公开(公告)号：US6141636A
公开(公告)日：2000-10-31
申请号：US831501
申请日：1997-03-31
申请人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Bernard Y. Chan , Michael C. Tsou
发明人： Tony R. Sarno , Ingo Schaefer , John E. Chilton , Mark S. Papamarcos , Bernard Y. Chan , Michael C. Tsou
IPC分类号： G06F17/50 , G06F11/25 , G06F11/26 , G06F11/34 , G06F9/455
CPC分类号： G06F11/261 , G06F11/25 , G06F11/3466
摘要： A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.
摘要翻译：时间分片仿真器中的逻辑分析子系统。逻辑分析子系统“重建”先前由编译器减少的信号，并允许用户使用仿真电路的这些和其他信号来设置断点和触发。本发明包括“逻辑分析子系统编译器”和“逻辑分析子系统硬件”。逻辑分析子系统编译器是常规仿真器编译器的子部分，也可以是独立编译器。它编译要仿真的设计，并为逻辑分析子系统硬件生成控制指令。逻辑分析子系统硬件被并入到时间分割的仿真器中，以在仿真期间接收由仿真器产生的信号。当逻辑分析子系统运行时，控制指令使逻辑分析子系统重建从仿真器接收的先前减小的信号。这些信号（以及从仿真器接收到的信号）可以由用户用于在逻辑分析子系统中设置断点和触发器。

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