会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Current/charge-voltage convertor
    • 电流/充电电压转换器
    • US20050105309A1
    • 2005-05-19
    • US10982209
    • 2004-11-05
    • Tomoya FujisakiMasaharu Goto
    • Tomoya FujisakiMasaharu Goto
    • G01R19/00G01R29/24G06G7/186H02M7/00H03F3/00
    • G01R29/24G01R19/0092
    • A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.
    • 一种具有运算放大器和连接在运算放大器的输入端和输出端之间的电容器的电流/电荷 - 电压转换电路,该电流/电荷 - 电压转换电路的特征在于,它包括相互连接的第一对二极管 与该输入端相反的方向,将第二对二极管与该第一对二极管的相反方向连接到该第一对二极管的相应另一个端子,一对电流源以相互相对的方向连接到相应的另一个端子 的第一对二极管,连接到该第一对二极管的另一个端子的一对开关,以及连接在该第二对二极管的相应另一个端子之间的电阻器。
    • 2. 发明授权
    • Current/charge-voltage converter
    • 电流/电荷电压转换器
    • US07057909B2
    • 2006-06-06
    • US10982209
    • 2004-11-05
    • Tomoya FujisakiMasaharu Goto
    • Tomoya FujisakiMasaharu Goto
    • H02M7/00
    • G01R29/24G01R19/0092
    • A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.
    • 一种具有运算放大器和连接在运算放大器的输入端和输出端之间的电容器的电流/电荷 - 电压转换电路,该电流/电荷 - 电压转换电路的特征在于,它包括相互连接的第一对二极管 与该输入端相反的方向,将第二对二极管与该第一对二极管的相反方向连接到该第一对二极管的相应另一个端子,一对电流源以相互相对的方向连接到相应的另一个端子 的第一对二极管,连接到该第一对二极管的另一个端子的一对开关,以及连接在该第二对二极管的相应另一个端子之间的电阻器。
    • 3. 发明授权
    • Timing adjustment circuit
    • 定时调整电路
    • US5589788A
    • 1996-12-31
    • US435877
    • 1995-05-05
    • Masaharu Goto
    • Masaharu Goto
    • G01R29/02G01R31/00G01R31/3183G01R31/319G06F1/10H03K5/13H03K5/135
    • G01R31/3191H03K5/131
    • A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements. When the active edge has arrived at each of the selection gates, each is held in an output state until the input to the selection gates becomes inactive, even if the selection signals changes.
    • 定时调整电路包括由串联连接的n个延迟元件(n为2以上的整数)构成的延迟电路,输入信号p0由各个延迟元件依次延迟,以产生相应的延迟元件, 信号p1,。 。 。 ,pn以及输入信号p0和上述各个延迟信号p1,...的选择电路。 。 。 ,pn由n + 1个选择信号s0,...选择。 。 。 ,sn。 选择电路包括选择信号生成电路,选择门电路,选择信号保持电路和延迟信号保持电路。 选择信号生成电路生成选择信号s0,...。 。 。 ,输入信号p0之前的sn。 选择信号保持电路保持选择信号s0,。 。 。 ,sn从选择信号发生电路直到p0的有效边沿。 。 。 ,pn到达每个选择门。 延迟信号保持电路包括n个延迟信号保持元件。 当有效边沿到达每个选择门时,即使选择信号改变,每个选择门都保持在输出状态,直到选择门的输入变为无效。
    • 7. 发明授权
    • Apparatus for testing and measuring electronic device and method of
calibrating its timing and voltage level
    • 用于测试和测量电子设备的装置及其时序和电压电平校准方法
    • US5712855A
    • 1998-01-27
    • US145419
    • 1993-10-29
    • Masaharu GotoKenichi Ito
    • Masaharu GotoKenichi Ito
    • G01R31/00G01R31/28G01R31/319G01R35/00G06K5/04G11B27/00
    • G01R35/00G01R31/3191
    • The present invention is intended to provide a testing and measuring apparatus for accurately and quickly calibrating the input and output timing of a plurality of test signal patterns and voltage levels. The invention also offers a method used for the calibration. The apparatus is equipped with a plurality of units (timing vector generators) each having a timing-generating circuit (a capture timing generator) and an external common reference timing circuit (a golden edge generator) outside the units. Each unit comprises: (1) a timing comparator circuit (a capture comparator) for comparing the timing each of the timing-generating circuits with the timing of the reference timing circuit to determine whether the former timing leads or lags the latter timing; and (2) a counter circuit which counts a number of comparisons made by the comparator circuit until their sequential relation has been reversed.
    • 本发明旨在提供一种用于准确且快速地校准多个测试信号模式和电压电平的输入和输出定时的测试和测量装置。 本发明还提供了用于校准的方法。 该装置配备有在单元外部具有定时发生电路(捕获定时发生器)和外部公共基准定时电路(金边缘发生器)的多个单元(定时矢量发生器)。 每个单元包括:(1)定时比较器电路(捕获比较器),用于将每个定时产生电路的定时与基准定时电路的定时进行比较,以确定前一个时序是否导通或落后于后一个定时; 以及(2)计数器电路,对由比较器电路进行的比较进行计数,直到它们的顺序关系被反转。
    • 8. 发明授权
    • CMOS pseudo-NMOS programmable capacitance time vernier and method of
calibration
    • CMOS伪NMOS可编程电容时间游标和校准方法
    • US5214680A
    • 1993-05-25
    • US786447
    • 1991-11-01
    • Alberto Gutierrez, Jr.Christopher KoernerMasaharu GotoJames O. Barnes
    • Alberto Gutierrez, Jr.Christopher KoernerMasaharu GotoJames O. Barnes
    • G01R31/319H03K5/00H03K5/13H03M1/66H03M1/68H03M1/74
    • H03M1/687G01R31/31922H03K5/131H03K5/133H03M1/66H03K2005/00097H03M1/745H03M1/747
    • The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges. Furthermore, the architecture of the present invention enables an automated method of calibration in order to adjust fine and coarse delay elements for fabrication process variations and photolithography variations.
    • 本发明是提供具有粗定时边缘的输入信号的精确定时控制的时间游标。 时间游标包括接收装置,用于接收表示要添加到粗时序边缘输入的期望时间延迟的值。 期望的时间延迟可以具有精细和粗略的延迟方面。 时间游标还包括用于解码精细延迟方面并产生精细延迟控制信号的第一解码装置,以及用于解码粗略延迟方面并产生粗略延迟控制信号的第二解码装置。 延时线还包括在时间游标中,其具有用于接收具有粗定时边缘的输入信号的输入,精细和粗略的延迟控制信号以及根据温度和电源变化自动调整的控制电压,以便提供 温度和电源补偿。 延迟线组合精细和粗略的延迟信号,以提供具有精细时序边缘的输出信号。 此外,本发明的架构能够实现自动校准方法,以便调整用于制造工艺变化和光刻变化的精细和粗略的延迟元件。
    • 9. 发明授权
    • Food preparation device
    • 食物制备装置
    • US08857747B2
    • 2014-10-14
    • US13374758
    • 2012-01-10
    • Masaharu Goto
    • Masaharu Goto
    • A47J43/25
    • A47J43/25
    • A food preparation plate is replaceable and engagement means for retaining the food preparation plate are present between the food preparation plate and a retaining part. The food preparation plate can move in translation in a direction perpendicular to a plane constituted by the retaining part. Two places on the back side of the food preparation plate that is retained in the retaining part can be simultaneously pressed in the direction of the front side by the digits of different hands; and by simultaneously pressing those two places with digits of different hands, the food preparation plate is moved in translation in the direction of the front side thereof, so as to release the engagement means and allow the food preparation plate to be detached.
    • 食品准备板是可替换的,并且用于保持食物制备板的接合装置存在于食物准备板和保持部分之间。 食物准备板可以在垂直于由保持部构成的平面的方向上平移移动。 保持在保持部上的食品准备板的背侧的两个位置可以通过不同的手的数字同时沿前侧的方向按压; 并且通过同时用不同手的数字按压这两个位置,使食物准备板沿其前侧的方向移动平移,以便释放接合装置并允许食物准备板被拆卸。