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1. 发明授权

US06415778B1 Breather chamber structure of internal combustion engine 有权
标题翻译：内燃机呼吸室结构
公开(公告)号：US06415778B1
公开(公告)日：2002-07-09
申请号：US09807957
申请日：2001-07-19
申请人： Hiroyuki Makino , Masaharu Goto , Yasuyo Kosugi , Shotaro Takano
发明人： Hiroyuki Makino , Masaharu Goto , Yasuyo Kosugi , Shotaro Takano
IPC分类号： F02M3510
CPC分类号： F01M13/04 , F01M5/021 , F01M2013/0027 , F01M2013/0455 , F01M2013/0472
摘要： A breather chamber structure of an internal combustion engine in which condensation of vapor within the breather chamber is prevented, the number of required parts is small, the space efficiency is superior and enlargement of the whole engine can be avoided is provided. In an internal combustion engine having auxiliary machinery attached to a side wall of a cylinder block (3) by means of an auxiliary machinery bracket (10), a breather chamber (20) is formed by the side wall of the cylinder block (3) and the auxiliary machinery bracket (10) between the side wall and the bracket, and a cooling water passage (40), (41) is formed on at least one of the side wall of the cylinder block (3) and the auxiliary machinery bracket (10) swelling in the breather chamber (20).
摘要翻译：一种内燃机的通气室结构，其中防止了通气室内的蒸汽冷凝，所需部件的数量小，空间效率优异，并且可以避免整个发动机的放大。在内燃具有通过辅助机械支架（10）附接到气缸体（3）的侧壁的辅助机械的发动机，通过气缸体（3）的侧壁和辅助机构形成的通气室（20）在侧壁和支架之间的支架（10）和在气缸体（3）的侧壁和辅助机械支架（10）中的至少一个上形成有膨胀的冷却水通道（40），（41）在通气室（20）中。

2. 发明授权

US06101995A Structure for mounting of auxiliary parts on in-line type multi-cylinder engine 失效
标题翻译：辅助部件安装在直列式多缸发动机上的结构
公开(公告)号：US06101995A
公开(公告)日：2000-08-15
申请号：US282433
申请日：1999-03-31
申请人： Kenji Itoh , Yasuyo Kosugi , Masaharu Goto
发明人： Kenji Itoh , Yasuyo Kosugi , Masaharu Goto
IPC分类号： F02B67/06 , F02B75/20 , F02F7/00
CPC分类号： F02B67/06 , F02B75/20
摘要： An auxiliary part mounting bracket for an in-line multi-cylinder engine. An oil pump, an auto-tensioner, an alternator, a water pump and a compressor are preassembled on the auxiliary part mounting bracket to form an assembly. This assembly is fixed to a side of the engine cylinder block by six bolts. One bolt is threadedly inserted into the cylinder block through a space defined between the upper oil pump and auto-tensioner and the lower alternator and water pump; two bolts are threadedly inserted into the cylinder block through a space defined between the upper positioned alternator and water pump and the lower positioned compressor. Thus, it is possible to enhance the assembling operation, when the plurality of auxiliary parts are fixed to an engine body through the auxiliary part mounting bracket.
摘要翻译：用于直列多缸发动机的辅助部件安装支架。油泵，自动张紧器，交流发电机，水泵和压缩机预先组装在辅助部件安装支架上以形成组件。该组件通过六个螺栓固定在发动机气缸体的一侧。一个螺栓通过上油泵和自动张紧器和下交流发电机和水泵之间的空间螺纹插入气缸体; 两个螺栓通过上定位的交流发电机和水泵与下部定位的压缩机之间的空间被螺纹地插入气缸体中。因此，当多个辅助部件通过辅助部件安装支架固定到发动机主体时，可以增强组装操作。

3. 发明申请

US20050105309A1 Current/charge-voltage convertor 有权
标题翻译：电流/充电电压转换器
公开(公告)号：US20050105309A1
公开(公告)日：2005-05-19
申请号：US10982209
申请日：2004-11-05
申请人： Tomoya Fujisaki , Masaharu Goto
发明人： Tomoya Fujisaki , Masaharu Goto
IPC分类号： G01R19/00 , G01R29/24 , G06G7/186 , H02M7/00 , H03F3/00
CPC分类号： G01R29/24 , G01R19/0092
摘要： A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.
摘要翻译：一种具有运算放大器和连接在运算放大器的输入端和输出端之间的电容器的电流/电荷 - 电压转换电路，该电流/电荷 - 电压转换电路的特征在于，它包括相互连接的第一对二极管与该输入端相反的方向，将第二对二极管与该第一对二极管的相反方向连接到该第一对二极管的相应另一个端子，一对电流源以相互相对的方向连接到相应的另一个端子的第一对二极管，连接到该第一对二极管的另一个端子的一对开关，以及连接在该第二对二极管的相应另一个端子之间的电阻器。

4. 发明授权

US5589788A Timing adjustment circuit 失效
标题翻译：定时调整电路
公开(公告)号：US5589788A
公开(公告)日：1996-12-31
申请号：US435877
申请日：1995-05-05
申请人： Masaharu Goto
发明人： Masaharu Goto
IPC分类号： G01R29/02 , G01R31/00 , G01R31/3183 , G01R31/319 , G06F1/10 , H03K5/13 , H03K5/135
CPC分类号： G01R31/3191 , H03K5/131
摘要： A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements. When the active edge has arrived at each of the selection gates, each is held in an output state until the input to the selection gates becomes inactive, even if the selection signals changes.
摘要翻译：定时调整电路包括由串联连接的n个延迟元件（n为2以上的整数）构成的延迟电路，输入信号p0由各个延迟元件依次延迟，以产生相应的延迟元件，信号p1，。。。，pn以及输入信号p0和上述各个延迟信号p1，...的选择电路。。。，pn由n + 1个选择信号s0，...选择。。。，sn。选择电路包括选择信号生成电路，选择门电路，选择信号保持电路和延迟信号保持电路。选择信号生成电路生成选择信号s0，...。。。，输入信号p0之前的sn。选择信号保持电路保持选择信号s0，。。。，sn从选择信号发生电路直到p0的有效边沿。。。，pn到达每个选择门。延迟信号保持电路包括n个延迟信号保持元件。当有效边沿到达每个选择门时，即使选择信号改变，每个选择门都保持在输出状态，直到选择门的输入变为无效。

5. 发明申请

US20110024163A1 Print Circuit Board With High Insulated Region, Method Of Manufacturing Thereof, And Print Circuit Board Assembly Thereof 有权
标题翻译：具有高绝缘区域的印刷电路板，其制造方法及其印刷电路板组件
公开(公告)号：US20110024163A1
公开(公告)日：2011-02-03
申请号：US12512029
申请日：2009-07-30
申请人： Masaharu Goto , Minoru Uchida , Koji Tokuno
发明人： Masaharu Goto , Minoru Uchida , Koji Tokuno
IPC分类号： H05K1/05 , H05K3/00 , H05K1/11
CPC分类号： H05K1/0256 , H05K1/181 , H05K2201/0723 , H05K2201/09036 , H05K2201/09072 , H05K2201/09972 , H05K2201/10166 , Y10T29/49155
摘要： A print circuit board includes: a first surface; a guard plane disposed on an inner layer; a high insulated region formed on the first surface of the board so as to be opposed to the guard plane, the high insulated region being substantially surrounded by one or more first guard patterns; and a quasi-high insulated region formed on the first surface of the board so as to be disposed adjacent to the high insulated region. The quasi-high insulated region is substantially surrounded by at least a part of the one or more first guard patterns and by one or more second guard patterns, in which the one or more first guard patterns and the one or more second guard patterns are each formed by forming one or more trenches in the first surface of the board so as to expose the guard plane on a bottom surface of the trenches.
摘要翻译：印刷电路板包括：第一表面; 设置在内层上的保护平面; 形成在所述基板的所述第一表面上以与所述保护平面相对的高绝缘区域，所述高绝缘区域基本上被一个或多个第一保护图案包围; 以及形成在所述基板的所述第一表面上以准备邻近所述高绝缘区域设置的准高绝缘区域。准高绝缘区域基本上由一个或多个第一保护图案的至少一部分和一个或多个第二保护图案包围，其中一个或多个第一保护图案和一个或多个第二保护图案各自通过在所述板的所述第一表面中形成一个或多个沟槽而形成，以便在所述沟槽的底表面上露出所述保护平面。

6. 发明申请

US20060041809A1 Method for optimizing a pattern generation program, a program, and a signal generator 失效
标题翻译：用于优化图案生成程序，程序和信号发生器的方法
公开(公告)号：US20060041809A1
公开(公告)日：2006-02-23
申请号：US11181955
申请日：2005-07-14
申请人： Masaru Shimura , Takuya Otani , Masaharu Goto
发明人： Masaru Shimura , Takuya Otani , Masaharu Goto
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31813 , G01R31/318314
摘要： A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, this optimizing method comprising an evaluation step for evaluating for each command of the pattern generation program whether it is necessary to develop the command in question of the program and a development step for developing the command.
摘要翻译：一种用于优化在信号发生器中使用的模式生成程序的方法，包括：发生器，用于基于模式产生程序产生信号模式;存储器，用于存储信号模式;以及输出，用于以预定周期输出由存储器，该优化方法包括用于评估图案生成程序的每个命令的评估步骤，是否需要开发所述程序的问题的命令以及用于开发命令的开发步骤。

7. 发明授权

US07404130B2 Method for optimizing a pattern generation program, a program, and a signal generator 失效
标题翻译：用于优化图案生成程序，程序和信号发生器的方法
公开(公告)号：US07404130B2
公开(公告)日：2008-07-22
申请号：US11181955
申请日：2005-07-14
申请人： Masaru Shimura , Takuya Otani , Masaharu Goto
发明人： Masaru Shimura , Takuya Otani , Masaharu Goto
IPC分类号： G01R31/28 , G06F9/44
CPC分类号： G01R31/31813 , G01R31/318314
摘要： A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, this optimizing method comprising an evaluation step for evaluating for each command of the pattern generation program whether it is necessary to develop the command in question of the program and a development step for developing the command.
摘要翻译：一种用于优化在信号发生器中使用的模式生成程序的方法，包括：发生器，用于基于模式产生程序产生信号模式;存储器，用于存储信号模式;以及输出，用于以预定周期输出由存储器，该优化方法包括用于评估图案生成程序的每个命令的评估步骤，是否需要开发所述程序的问题的命令以及用于开发命令的开发步骤。

8. 发明授权

US07057909B2 Current/charge-voltage converter 有权
标题翻译：电流/电荷电压转换器
公开(公告)号：US07057909B2
公开(公告)日：2006-06-06
申请号：US10982209
申请日：2004-11-05
申请人： Tomoya Fujisaki , Masaharu Goto
发明人： Tomoya Fujisaki , Masaharu Goto
IPC分类号： H02M7/00
CPC分类号： G01R29/24 , G01R19/0092
摘要： A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.
摘要翻译：一种具有运算放大器和连接在运算放大器的输入端和输出端之间的电容器的电流/电荷 - 电压转换电路，该电流/电荷 - 电压转换电路的特征在于，它包括相互连接的第一对二极管与该输入端相反的方向，将第二对二极管与该第一对二极管的相反方向连接到该第一对二极管的相应另一个端子，一对电流源以相互相对的方向连接到相应的另一个端子的第一对二极管，连接到该第一对二极管的另一个端子的一对开关，以及连接在该第二对二极管的相应另一个端子之间的电阻器。

9. 发明授权

US5712855A Apparatus for testing and measuring electronic device and method of calibrating its timing and voltage level 失效
标题翻译：用于测试和测量电子设备的装置及其时序和电压电平校准方法
公开(公告)号：US5712855A
公开(公告)日：1998-01-27
申请号：US145419
申请日：1993-10-29
申请人： Masaharu Goto , Kenichi Ito
发明人： Masaharu Goto , Kenichi Ito
IPC分类号： G01R31/00 , G01R31/28 , G01R31/319 , G01R35/00 , G06K5/04 , G11B27/00
CPC分类号： G01R35/00 , G01R31/3191
摘要： The present invention is intended to provide a testing and measuring apparatus for accurately and quickly calibrating the input and output timing of a plurality of test signal patterns and voltage levels. The invention also offers a method used for the calibration. The apparatus is equipped with a plurality of units (timing vector generators) each having a timing-generating circuit (a capture timing generator) and an external common reference timing circuit (a golden edge generator) outside the units. Each unit comprises: (1) a timing comparator circuit (a capture comparator) for comparing the timing each of the timing-generating circuits with the timing of the reference timing circuit to determine whether the former timing leads or lags the latter timing; and (2) a counter circuit which counts a number of comparisons made by the comparator circuit until their sequential relation has been reversed.
摘要翻译：本发明旨在提供一种用于准确且快速地校准多个测试信号模式和电压电平的输入和输出定时的测试和测量装置。本发明还提供了用于校准的方法。该装置配备有在单元外部具有定时发生电路（捕获定时发生器）和外部公共基准定时电路（金边缘发生器）的多个单元（定时矢量发生器）。每个单元包括：（1）定时比较器电路（捕获比较器），用于将每个定时产生电路的定时与基准定时电路的定时进行比较，以确定前一个时序是否导通或落后于后一个定时; 以及（2）计数器电路，对由比较器电路进行的比较进行计数，直到它们的顺序关系被反转。

10. 发明授权

US5214680A CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration 失效
标题翻译： CMOS伪NMOS可编程电容时间游标和校准方法
公开(公告)号：US5214680A
公开(公告)日：1993-05-25
申请号：US786447
申请日：1991-11-01
申请人： Alberto Gutierrez, Jr. , Christopher Koerner , Masaharu Goto , James O. Barnes
发明人： Alberto Gutierrez, Jr. , Christopher Koerner , Masaharu Goto , James O. Barnes
IPC分类号： G01R31/319 , H03K5/00 , H03K5/13 , H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/687 , G01R31/31922 , H03K5/131 , H03K5/133 , H03M1/66 , H03K2005/00097 , H03M1/745 , H03M1/747
摘要： The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges. Furthermore, the architecture of the present invention enables an automated method of calibration in order to adjust fine and coarse delay elements for fabrication process variations and photolithography variations.
摘要翻译：本发明是提供具有粗定时边缘的输入信号的精确定时控制的时间游标。时间游标包括接收装置，用于接收表示要添加到粗时序边缘输入的期望时间延迟的值。期望的时间延迟可以具有精细和粗略的延迟方面。时间游标还包括用于解码精细延迟方面并产生精细延迟控制信号的第一解码装置，以及用于解码粗略延迟方面并产生粗略延迟控制信号的第二解码装置。延时线还包括在时间游标中，其具有用于接收具有粗定时边缘的输入信号的输入，精细和粗略的延迟控制信号以及根据温度和电源变化自动调整的控制电压，以便提供温度和电源补偿。延迟线组合精细和粗略的延迟信号，以提供具有精细时序边缘的输出信号。此外，本发明的架构能够实现自动校准方法，以便调整用于制造工艺变化和光刻变化的精细和粗略的延迟元件。

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