专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140344115A1 PRODUCT SEARCH SYSTEM 审中-公开
标题翻译：产品搜索系统
公开(公告)号：US20140344115A1
公开(公告)日：2014-11-20
申请号：US14368305
申请日：2012-02-06
申请人： Tomoko Yatsuda , Takeshi Nagai , Takeshi Kasamaki , Katsuhiro Suzuki
发明人： Tomoko Yatsuda , Takeshi Nagai , Takeshi Kasamaki , Katsuhiro Suzuki
IPC分类号： G06F17/30 , G06Q30/06
CPC分类号： G06F16/248 , G06F16/26 , G06F16/951 , G06Q30/0627 , G06Q30/0629
摘要： A product search system includes a product data storage portion for storing product data, an axis item data storage portion for storing settability information for axis items and axis division numbers, a product ID storage portion for storing unique identification information of products, a two-dimensional coordinate space defining portion for defining a two-dimensional coordinate space, a distribution diagram generating portion for generating data for a distribution diagram in which product images are arranged in the coordinate space, and a product extracting portion for extracting unique identification information of products within an area of a section selected by a user, and storing the information in the product ID storage portion. Once the unique identification information is stored in the product ID storage portion, the distribution diagram generating portion generates data for a post-refinement distribution diagram in which product images for products corresponding to the stored unique identification information are relatively highlighted.
摘要翻译：产品搜索系统包括用于存储产品数据的产品数据存储部分，用于存储用于轴项目和轴分配数字的可设置性信息的轴项目数据存储部分，用于存储产品的唯一标识信息的产品ID存储部分，二维用于定义二维坐标空间的坐标空间限定部分，用于生成其中在坐标空间中排列产品图像的分布图的数据的分布图生成部分，以及用于提取在坐标空间内的产品的唯一识别信息的产品提取部分区域，并将该信息存储在产品ID存储部分中。一旦将唯一的识别信息存储在产品ID存储部分中，分发图生成部分生成后期细化分布图的数据，其中与所存储的唯一标识信息相对应的产品的商品图像被相对突出显示。

2. 发明申请

US20070061678A1 Coding system and decoding system 失效
标题翻译：编码系统和解码系统
公开(公告)号：US20070061678A1
公开(公告)日：2007-03-15
申请号：US11584583
申请日：2006-10-23
申请人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
发明人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G11B20/1813 , G11B27/3027 , H03M13/15 , H03M13/152 , H03M13/23 , H03M13/33 , H03M13/356 , H04J3/0602 , H04L1/0041 , H04L1/0047 , H04L1/0068 , H04L1/007 , H04L1/0075 , H04L1/0079 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/68 , H04N19/70 , H04N19/89
摘要： In a coding system where in an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
摘要翻译：在将错误校正/检测编码与使用同步码的同步恢复技术组合的编码系统中，解决了由于错误检测引起的伪同步和失步的问题。提供了编码部分212，用于将输入的多路复用代码串201编码到包括信息位和校验位的纠错/检测码，以及代码串组合部分213，用于将同步码插入到多个在代码串201中周期性地预定的同步代码插入位置，用于将信息位布置在代码串中的可选位置处，并且用于将校验位排列在代码串201中的同步代码插入位置以外的位置，以组合输出代码串205。

3. 发明申请

US20070061679A1 Coding system and decoding system 审中-公开
标题翻译：编码系统和解码系统
公开(公告)号：US20070061679A1
公开(公告)日：2007-03-15
申请号：US11584584
申请日：2006-10-23
申请人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
发明人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G11B20/1813 , G11B27/3027 , H03M13/15 , H03M13/152 , H03M13/23 , H03M13/33 , H03M13/356 , H04J3/0602 , H04L1/0041 , H04L1/0047 , H04L1/0068 , H04L1/007 , H04L1/0075 , H04L1/0079 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/68 , H04N19/70 , H04N19/89
摘要： In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
摘要翻译：在其中纠错/检测编码与使用同步码的同步恢复技术组合的编码系统中，解决了由于错误检测引起的伪同步和失步的问题。提供了一个用于将输入的多路复用代码串201编码到包括信息位和校验位的纠错/检测码的编码部分212，以及代码串组合部分213，用于将同步码插入多个周期性的任一个代码串201中的预定同步代码插入位置，用于将信息位布置在代码串中的可选位置处，并且用于将校验位排列在代码串201中的同步代码插入位置以外的位置，以组合输出代码串205。

4. 发明授权

US08395197B2 Semiconductor device and method of forming the same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US08395197B2
公开(公告)日：2013-03-12
申请号：US12961252
申请日：2010-12-06
申请人： Takeshi Nagai
发明人： Takeshi Nagai
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L31/062 , H01L31/113
CPC分类号： H01L27/10894 , H01L21/823412 , H01L21/823418 , H01L27/10873 , H01L27/10876 , H01L29/4236 , H01L29/6659 , H01L29/66621 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device includes a gate electrode on a gate insulating film over a semiconductor substrate, a first sidewall insulating film on a side surface of the gate electrode, and source and drain regions, each including a pocket diffusion layer of a first conductivity type, and first and second diffusion layers of a second conductivity type. The pocket diffusion layer is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer over the first diffusion layer is higher in impurity concentration than the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer, and has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.
摘要翻译：半导体器件包括在半导体衬底上的栅极绝缘膜上的栅电极，栅电极的侧表面上的第一侧壁绝缘膜，以及源极和漏极区，每个包括第一导电类型的穴扩散层，以及第二导电类型的第一和第二扩散层。该袋扩散层设置在半导体衬底中。第二导电类型的第一扩散层在袋扩散层上延伸。第一扩散层通过第一侧壁绝缘膜朝向栅电极。第一扩散层上的第二扩散层的杂质浓度高于第一扩散层。第二扩散层通过第一扩散层从袋扩散层分离，并且具有通过第一扩散层面向第一侧壁绝缘膜的侧表面。

5. 再颁专利

USRE42474E1 Moving-picture signal coding and/or decoding system resistant to transmission error 有权
公开(公告)号：USRE42474E1
公开(公告)日：2011-06-21
申请号：US12762935
申请日：2010-04-19
申请人： Takeshi Nagai , Kenshi Dachiku , Takeshi Chujoh , Yoshihiro Kikuchi , Toshiaki Watanabe
发明人： Takeshi Nagai , Kenshi Dachiku , Takeshi Chujoh , Yoshihiro Kikuchi , Toshiaki Watanabe
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/61 , H04N19/46
摘要： An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the additional code string by a code-string synthesizer to be outputted as an output code string. Thus, there is provided an image data coding system which can quickly restore data even if the data is lost due to error and in which the increased code amount is less than the cycle refresh and the error correction.

6. 再颁专利

USRE42456E1 Moving-picture signal coding and/or decoding system resistant to transmission error 有权
公开(公告)号：USRE42456E1
公开(公告)日：2011-06-14
申请号：US12762983
申请日：2010-04-19
申请人： Takeshi Nagai , Kenshi Dachiku , Takeshi Chujoh , Yoshihiro Kikuchi , Toshiaki Watanabe
发明人： Takeshi Nagai , Kenshi Dachiku , Takeshi Chujoh , Yoshihiro Kikuchi , Toshiaki Watanabe
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/61 , H04N19/46
摘要： An input image signal is coded by an encoder to be outputted as a basic code string, and the basic code string is delayed by a code-string delay circuit for a predetermined period of time to be outputted as an additional code string. The basic code string is synthesized with the additional code string by a code-string synthesizer to be outputted as an output code string. Thus, there is provided an image data coding system which can quickly restore data even if the data is lost due to error and in which the increased code amount is less than the cycle refresh and the error correction.

7. 发明申请

US20100232808A1 RECEIVING CIRCUIT FOR OPTICAL COMMUNICATION 失效
标题翻译：接收电路用于光通信
公开(公告)号：US20100232808A1
公开(公告)日：2010-09-16
申请号：US12555995
申请日：2009-09-09
申请人： Takeshi Nagai
发明人： Takeshi Nagai
IPC分类号： H04B10/06
CPC分类号： H04B10/697
摘要： A receiving circuit for optical communication includes: a differential circuit, one differential input terminal of which is connected to an anode side of a first photodiode and the other differential input terminal of which is connected to an anode side of a second photodiode; a latch circuit that performs latch operation based on output of the differential circuit; and a flip-flop that performs set operation and reset operation based on a latch state of the latch circuit.
摘要翻译：一种用于光通信的接收电路包括：差分电路，其一个差分输入端连接到第一光电二极管的阳极侧，另一个差分输入端连接到第二光电二极管的阳极侧; 锁存电路，其基于差分电路的输出进行锁存动作; 以及触发器，其基于锁存电路的锁存状态执行设定操作和复位操作。

8. 发明授权

US07610542B2 Semiconductor memory in which error correction is performed by on-chip error correction circuit 失效
标题翻译：半导体存储器，其中通过片上纠错电路进行纠错
公开(公告)号：US07610542B2
公开(公告)日：2009-10-27
申请号：US11454007
申请日：2006-06-16
申请人： Takeshi Nagai
发明人： Takeshi Nagai
IPC分类号： G11C29/00
CPC分类号： G11C7/1039 , G06F11/1008 , G11C7/1006 , G11C11/4096 , G11C2029/0411 , G11C2207/104
摘要： A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected by the error correction circuit, and write the overwritten data in the memory cell. The output circuit is configured to output the overwritten data outside a chip. The second write circuit is configured to reoverwrite at least a portion of write data which is externally input at a different time on the overwritten data, encode the reoverwritten data, and write the encoded data in the memory cell.
摘要翻译：执行流水线操作的同步半导体存储器包括纠错电路，输出电路以及第一和第二写入电路。第一写入电路被配置为覆盖从存储器单元读出并由纠错电路校正的数据的外部输入写入数据的至少一部分，并将重写的数据写入存储单元。输出电路被配置为输出芯片外部的重写数据。第二写入电路被配置为重新写入写入数据的至少一部分，该写入数据在重写的数据上以不同的时间被外部输入，对重写的数据进行编码，并将编码的数据写入存储单元。

9. 发明授权

US07502975B2 Data transmission apparatus and method 失效
公开(公告)号：US07502975B2
公开(公告)日：2009-03-10
申请号：US11755622
申请日：2007-05-30
申请人： Takeshi Nagai , Yoshihiro Kikuchi , Tadaaki Masuda
发明人： Takeshi Nagai , Yoshihiro Kikuchi , Tadaaki Masuda
IPC分类号： G01R31/28
CPC分类号： H04N21/6377 , H04L1/0002 , H04L1/0009 , H04L1/0014 , H04L1/0015 , H04L1/0019 , H04L1/0026 , H04L1/205 , H04L47/10 , H04L47/11 , H04L47/25 , H04L47/283 , H04N21/658
摘要： A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

10. 发明授权

US07496807B2 Data transmission apparatus and method 失效
公开(公告)号：US07496807B2
公开(公告)日：2009-02-24
申请号：US11755616
申请日：2007-05-30
申请人： Takeshi Nagai , Yoshihiro Kikuchi , Tadaaki Masuda
发明人： Takeshi Nagai , Yoshihiro Kikuchi , Tadaaki Masuda
IPC分类号： G01R31/28
CPC分类号： H04N21/6377 , H04L1/0002 , H04L1/0009 , H04L1/0014 , H04L1/0015 , H04L1/0019 , H04L1/0026 , H04L1/205 , H04L47/10 , H04L47/11 , H04L47/25 , H04L47/283 , H04N21/658
摘要： A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式