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1. 发明授权

US5237667A Digital signal processor system having host processor for writing instructions into internal processor memory 失效
标题翻译：数字信号处理器系统具有用于将指令写入内部处理器存储器的主处
公开(公告)号：US5237667A
公开(公告)日：1993-08-17
申请号：US755503
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译：一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线，地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元执行阶段

2. 发明授权

US5045993A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：US5045993A
公开(公告)日：1991-09-03
申请号：US201208
申请日：1988-06-03
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/345 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/345 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

3. 发明授权

US5206940A Address control and generating system for digital signal-processor 失效
标题翻译：数字信号处理器的地址控制和发生系统
公开(公告)号：US5206940A
公开(公告)日：1993-04-27
申请号：US750512
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译：一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线，地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元执行阶段

4. 发明授权

US5247627A Digital signal processor with conditional branch decision unit and storage of conditional branch decision results 失效
标题翻译：具有条件分支决策单元的数字信号处理器和条件分支决策结果的存储
公开(公告)号：US5247627A
公开(公告)日：1993-09-21
申请号：US750478
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译：一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线，地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元执行阶段

5. 发明授权

US5222241A Digital signal processor having duplex working registers for switching to standby state during interrupt processing 失效
标题翻译：具有双工工作寄存器的数字信号处理器，用于在中断处理期间切换到待机状态
公开(公告)号：US5222241A
公开(公告)日：1993-06-22
申请号：US750408
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译：一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线，地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元执行阶段

6. 发明授权

US5161247A Digital signal processor matching data blocks against a reference block and replacing the reference block when a new minimum distortion block is calculated 失效
标题翻译：数字信号处理器匹配参考块的数据块，并在计算新的最小失真块时更换参考块
公开(公告)号：US5161247A
公开(公告)日：1992-11-03
申请号：US379274
申请日：1989-07-13
申请人： Tokumichi Murakami , Koh Kamizawa , Naoto Kinjo , Hideo Ohira , Takao Wakabayashi
发明人： Tokumichi Murakami , Koh Kamizawa , Naoto Kinjo , Hideo Ohira , Takao Wakabayashi
IPC分类号： G06T7/20 , H04N5/14 , H04N7/26
CPC分类号： G06T7/202 , G06T7/2013 , G06T7/2026 , H04N19/43 , H04N19/433 , H04N19/51 , H04N19/533 , H04N5/145 , G06T2200/28 , G06T2207/10016
摘要： The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reducing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.
摘要翻译：本发明改进了数字信号处理器，更具体地，涉及当在最后帧块和当前帧块之间的失真量时减少计算所需量的运动补偿的计算方法; 在更高效率地处理直接存储器访问; 在更高速度处理细分数据计算; 在管理过程中以更高的效率处理分支指令; 并且在更加方便的情况下处理在重复处理操作中发生的中断，并且还通过层级化的最小失真搜索处理来减少所需的计算量。

7. 发明授权

US5130797A Digital signal processing system for parallel processing of subsampled data 失效
标题翻译：用于并行处理子采样数据的数字信号处理系统
公开(公告)号：US5130797A
公开(公告)日：1992-07-14
申请号：US483840
申请日：1990-02-23
申请人： Tokumichi Murakami , Koh Kamizawa , Hideo Ohira , Kohji Ogura , Naoto Kinjo , Takao Wakabayashi
发明人： Tokumichi Murakami , Koh Kamizawa , Hideo Ohira , Kohji Ogura , Naoto Kinjo , Takao Wakabayashi
IPC分类号： H04N7/26 , H04N7/36 , H04N7/46
CPC分类号： H04N19/00 , H04N19/43 , H04N19/436 , H04N19/51 , H04N19/533 , H04N19/577 , H04N19/587 , H04N19/30
摘要： A video codec system inputs consecutively frame after frame of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each piece of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.
摘要翻译：视频编解码器系统以帧为单位对视频数据进行子采样而获得的子采样视频数据的帧后连续输入。视频数据由内部编码电路并行编码。这将对待处理的子采样视频数据中的有效像素数进行平均。编码视频数据被构成为符合接收设备的规格。在发送时，根据接收侧的编码电路的数量再次对数据进行子采样。给每个子采样数据提供连续传输的报头。这允许在到达接收侧的数据段之间的一定时间段，从而消除接收和编码中的时间差异。

8. 发明授权

US5155852A Digital information coding system which evenly distributes valid input data to digital signal processors operating in parallel 失效
标题翻译：数字信息编码系统，甚至可以将有效的输入数据分配给数字信号处理器并行运行
公开(公告)号：US5155852A
公开(公告)日：1992-10-13
申请号：US311815
申请日：1989-02-17
申请人： Tokumichi Murakami , Koh Kamizawa , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Naoto Kinjo
IPC分类号： G06F9/50 , G06T7/20 , H04N7/26 , H04N7/50
CPC分类号： G06F9/505 , G06F9/5066 , G06T7/2013 , H04N19/42 , H04N19/43 , H04N19/433 , H04N19/51 , H04N19/61 , G06T2207/10016 , H04N19/30
摘要： A digital signal processing apparatus which is used for the computation of coding image signals or the like and a motion compensative operation method which uses a digital signal processing apparatus. The apparatus comprises a plurality of signal processing means arranged in parallel and control means which assigns loads to the signal processing means so that the signal processing means have even computation volumes. Alternatively, an address generator is provided for each of data sets entered independently. An intermediate check is conducted during the computation for a block which involves a motion compensative operation.
摘要翻译：用于计算编码图像信号等的数字信号处理装置和使用数字信号处理装置的运动补偿运算方法。该装置包括并行布置的多个信号处理装置和向信号处理装置分配负载的控制装置，使得信号处理装置具有均匀的计算量。或者，为独立输入的每个数据集提供地址发生器。在涉及运动补偿操作的块的计算期间进行中间检查。

9. 再颁专利

USRE34850E Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：USRE34850E
公开(公告)日：1995-02-07
申请号：US803457
申请日：1991-12-06
申请人： Tokumichi Murakami , Koh Kamizawa , Masatoshi Kameyama
发明人： Tokumichi Murakami , Koh Kamizawa , Masatoshi Kameyama
IPC分类号： G06F15/16 , G06F9/32 , G06F13/28 , G06F15/167 , G06F15/78 , G06F15/80 , G06F17/10 , G06T1/00 , H03H17/02 , G06F13/14
CPC分类号： G06F13/28 , G06F15/7857
摘要： A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.
摘要翻译：数字信号处理器包括总线结构，包括程序总线，数据总线和数据输入/输出总线，程序存储器，程序控制器，由用于存储块数据的多个2-端口存储器构成的内部数据存储器，算术运算器，用于在算术运算器的内部操作中并行地实现内部数据存储器和外部数据存储器之间的块数据输入/输出的DMA控制器，用于同时产生用于内部操作和DMA传输的地址的地址生成器与内部操作并行的并行数据输入/输出端口，用于独立于输入/输出操作和异步方式实现与外部设备的并行数据通信。处理器执行复杂的自适应处理算法，例如高速和高吞吐量的图像信号处理。

10. 发明授权

US4920480A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：US4920480A
公开(公告)日：1990-04-24
申请号：US164257
申请日：1988-03-04
申请人： Tokumichi Murakami , Koh Kamizawa , Masatoshi Kameyama
发明人： Tokumichi Murakami , Koh Kamizawa , Masatoshi Kameyama
IPC分类号： G06F15/16 , G06F9/32 , G06F13/28 , G06F15/167 , G06F15/78 , G06F15/80 , G06F17/10 , G06T1/00 , H03H17/02
CPC分类号： G06F13/28 , G06F15/7857
摘要： A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.

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