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1. 发明授权

US06449702B1 Memory bandwidth utilization through multiple priority request policy for isochronous data streams 有权
标题翻译：通过用于等时数据流的多重优先级请求策略的内存带宽利用率
公开(公告)号：US06449702B1
公开(公告)日：2002-09-10
申请号：US09475732
申请日：1999-12-30
申请人： Todd M. Witter , Aditya Sreenivas , Sam Jensen
发明人： Todd M. Witter , Aditya Sreenivas , Sam Jensen
IPC分类号： G06F1216
CPC分类号： G06F13/1642
摘要： An embodiment of a system logic device for improving memory bandwidth utilization in a computer system with an isochronous data stream includes a FIFO for the isochronous data stream. The FIFO includes two watermarks. When the data level of the FIFO falls below a first watermark level, a low priority request is issued to a memory controller. If the data level of the FIFO falls below a second watermark level, a high priority memory request is issued to the memory controller. The low priority memory request is assigned the lowest priority level by the memory controller. The high priority request is assigned the highest priority level by the memory controller. The low priority request allows the isochronous data stream to retrieve small amounts of data from memory without negatively impacting overall system performance while the high priority request allows the isochronous data stream to retrieve larger amounts of data from memory within a fixed time in order to ensure that the FIFO never completely drains.
摘要翻译：用于提高具有同步数据流的计算机系统中的存储器带宽利用率的系统逻辑设备的实施例包括用于同步数据流的FIFO。 FIFO包括两个水印。当FIFO的数据电平低于第一水印级别时，向存储器控制器发出低优先级请求。如果FIFO的数据级别低于第二水印级别，则向存储器控制器发出高优先级的存储器请求。低优先级存储器请求由存储器控制器分配给最低优先级。高优先级请求由内存控制器分配最高优先级。低优先级请求允许等时数据流从存储器检索少量数据，而不会不利地影响整个系统性能，而高优先级请求允许等时数据流在固定时间内从存储器检索更大量的数据，以确保 FIFO从来没有完全排水。

2. 发明授权

US06629253B1 System for efficient management of memory access requests from a planar video overlay data stream using a time delay 失效
标题翻译：用于使用时间延迟从平面视频覆盖数据流高效地管理存储器访问请求的系统
公开(公告)号：US06629253B1
公开(公告)日：2003-09-30
申请号：US09475735
申请日：1999-12-30
申请人： Todd M. Witter , Aditya Sreenivas , Kim Meinerth
发明人： Todd M. Witter , Aditya Sreenivas , Kim Meinerth
IPC分类号： G06F104
CPC分类号： G06F3/14
摘要： A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.
摘要翻译：公开了一种用于管理覆盖数据请求的方法和装置。装置的一个实施例包括请求单元和定时器。图形控制器向请求单元请求一行覆盖数据。请求单元将请求从图形控制器分成一系列较小的请求。向内存控制器发出较小的请求。在每个较小的请求之间插入延迟，以便允许其他系统资源更容易地访问内存。

3. 发明授权

US07120774B2 Efficient management of memory access requests from a video data stream 失效
标题翻译：从视频数据流高效地管理存储器访问请求
公开(公告)号：US07120774B2
公开(公告)日：2006-10-10
申请号：US10672328
申请日：2003-09-26
申请人： Todd M. Witter , Aditya Sreenivas , Kim Meinerth
发明人： Todd M. Witter , Aditya Sreenivas , Kim Meinerth
IPC分类号： G06F12/00
CPC分类号： G06F3/14
摘要： A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.
摘要翻译：公开了一种用于管理覆盖数据请求的方法和装置。装置的一个实施例包括请求单元和定时器。图形控制器向请求单元请求一行覆盖数据。请求单元将请求从图形控制器分成一系列较小的请求。向内存控制器发出较小的请求。在每个较小的请求之间插入延迟，以便允许其他系统资源更容易地访问内存。

4. 发明申请

US20100027790A1 METHODS FOR AUTHENTICATING A HARDWARE DEVICE AND PROVIDING A SECURE CHANNEL TO DELIVER DATA 审中-公开
标题翻译：用于认证硬件设备并提供安全通道以提供数据的方法
公开(公告)号：US20100027790A1
公开(公告)日：2010-02-04
申请号：US11961848
申请日：2007-12-20
申请人： Balaji Vembu , Gary Graunke , Sathyamurthi Sadhasivan , Aditya Sreenivas
发明人： Balaji Vembu , Gary Graunke , Sathyamurthi Sadhasivan , Aditya Sreenivas
IPC分类号： H04N7/167 , H04L9/08
CPC分类号： G06F21/606
摘要： A method for delivering audio/video data through a hardware device using a software application comprises, at the hardware end, receiving an encrypted application key, an encrypted random session key, and encrypted audio/video data from the software. The hardware then decrypts the encrypted application key using a secret encryption key, decrypts the encrypted random session key using the application key, and decrypts the encrypted audio/video data using the random session key. The hardware may then deliver the unencrypted audio/video data by way of a display and speakers. The secret encryption key is securely embedded within the hardware device at an earlier point in time.
摘要翻译：通过使用软件应用的硬件设备来传送音频/视频数据的方法包括在硬件端从软件接收加密的应用密钥，加密的随机会话密钥和加密的音频/视频数据。然后硬件使用秘密加密密钥解密加密的应用密钥，使用应用密钥对加密的随机会话密钥进行解密，并使用随机会话密钥解密加密的音频/视频数据。然后硬件可以通过显示器和扬声器传递未加密的音频/视频数据。秘密加密密钥在较早的时间点安全地嵌入硬件设备内。

5. 发明授权

US06747657B2 Depth write disable for zone rendering 有权
公开(公告)号：US06747657B2
公开(公告)日：2004-06-08
申请号：US10038814
申请日：2001-12-31
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G06F1300
CPC分类号： G06T1/60 , G06T15/405
摘要： A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

6. 发明授权

US6078339A Mutual exclusion of drawing engine execution on a graphics device 失效
标题翻译：在图形设备上相互排除绘图引擎执行
公开(公告)号：US6078339A
公开(公告)日：2000-06-20
申请号：US21490
申请日：1998-02-10
申请人： Kim A. Meinerth , Aditya Sreenivas , Krishnan Sreenivas
发明人： Kim A. Meinerth , Aditya Sreenivas , Krishnan Sreenivas
IPC分类号： G06T1/20 , G06F15/00
CPC分类号： G06T1/20
摘要： A method for mutual exclusion of drawing engine execution on a graphics device is disclosed. The method checks a busy signal of an executing drawing engine. The executing drawing engine is one of a plurality of drawing engines of the graphics device and the only drawing engine executing out of the plurality of drawing engines. The method forwards a graphics instruction and associated data packet to a next drawing engine to execute after the executing drawing engine has completed execution. The next drawing engine to execute is one of the plurality of drawing engines.
摘要翻译：公开了一种在图形设备上相互排除绘图引擎执行的方法。该方法检查执行绘图引擎的忙信号。执行绘图引擎是图形装置的多个绘图引擎和从多个绘图引擎执行的唯一绘图引擎之一。该方法将图形指令和相关联的数据包转发到下一个绘图引擎，以便在执行绘图引擎完成执行后执行。下一个要执行的绘图引擎是多个绘图引擎之一。

7. 发明授权

US5696768A Method and apparatus for data storage array tracking 失效
标题翻译：数据存储阵列跟踪的方法和装置
公开(公告)号：US5696768A
公开(公告)日：1997-12-09
申请号：US763963
申请日：1996-12-10
申请人： David J. Harriman , Aditya Sreenivas , Russell W. Dyer
发明人： David J. Harriman , Aditya Sreenivas , Russell W. Dyer
IPC分类号： G06F5/10 , G06F11/00
CPC分类号： G06F5/10
摘要： A data storage array is provided having a number, n, of sequential data storage areas for the storage of data. A valid status array including n bits is provided where there is a one to one correspondence between the bits of the valid status array and the data storage areas of the data storage array. When valid data are written into a data storage area, the status bit of the valid status array corresponding to this data storage area is set to indicate that valid data are present. When data are read out of the data storage area, the corresponding status bit is cleared indicating the absence of valid data. If the data storage array is one that is written to in a random access manner and read from sequentially, as a queue, then the valid status array would indicate the presence of valid data at the head of the queue for the data storage array.
摘要翻译：提供了具有用于存储数据的数量为n的顺序数据存储区域的数据存储阵列。提供包括n位的有效状态阵列，其中在有效状态阵列的位和数据存储阵列的数据存储区之间存在一对一的对应关系。当有效数据被写入数据存储区域时，与该数据存储区域对应的有效状态阵列的状态位被设置为指示存在有效数据。当从数据存储区读出数据时，清除相应的状态位，指示不存在有效数据。如果数据存储阵列是以随机存取方式写入并以顺序读取的数据存储阵列作为队列，则有效状态阵列将指示在数据存储阵列的队列头部存在有效数据。

8. 发明申请

US20090172331A1 Securing content for playback 审中-公开
标题翻译：保护播放内容
公开(公告)号：US20090172331A1
公开(公告)日：2009-07-02
申请号：US12006282
申请日：2007-12-31
申请人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
发明人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
IPC分类号： G06F21/00
CPC分类号： G06F21/84 , G06F21/10 , G06F21/74
摘要： A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may access the encrypted material, decrypt the material, and provide it to the renderer engine of a graphics engine. The graphics engine may then process the decrypted material using the protected portion of the memory. Only graphics devices can access the protected portion of the memory in at least one mode, preventing access by outside sources. In addition, the protected memory may be stolen memory that is not identified to the operating system, making that stolen memory inaccessible to applications running on the operating system.
摘要翻译：图形引擎可以包括全部连接到显示器的解密设备，渲染器和子画面或覆盖引擎。在一个实施例中，存储器可以具有受保护和非保护部分。应用可以将加密的内容存储在所述存储器的非保护部分上。解密设备可以访问加密的材料，解密材料，并将其提供给图形引擎的渲染器引擎。然后，图形引擎可以使用存储器的受保护部分来处理解密的材料。只有图形设备才能以至少一种模式访问存储器的受保护部分，从而防止外部源的访问。此外，受保护的存储器可能是未被识别到操作系统的被盗存储器，使得被盗的存储器不能在操作系统上运行的应用程序访问。

9. 发明授权

US07321369B2 Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device 有权
标题翻译：用于在图形控制器设备上同步多个异步客户端队列的处理的方法和装置
公开(公告)号：US07321369B2
公开(公告)日：2008-01-22
申请号：US10232285
申请日：2002-08-30
申请人： David A. Wyatt , Aditya Sreenivas
发明人： David A. Wyatt , Aditya Sreenivas
IPC分类号： G09G5/36 , G06F1/00
CPC分类号： G06F9/3851 , G06F9/3879 , G06T15/005
摘要： An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should have processing suspended until a specified event condition occurs. Upon satisfaction of the specified condition, processing of commands from the suspended queue is resumed.
摘要翻译：公开了用于从多个命令队列同步命令处理的装置和方法。各种实施例使用条件码寄存器，其指示哪些队列应该具有暂停的处理，直到发生指定的事件条件。满足指定条件后，恢复从挂起的队列处理命令。

10. 发明申请

US20070188508A1 Optimized memory addressing 有权
公开(公告)号：US20070188508A1
公开(公告)日：2007-08-16
申请号：US11784342
申请日：2007-04-06
申请人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G09G5/399
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

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