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1. 发明授权

US5860128A Method and apparatus for sampling data from a memory 失效
标题翻译：用于从存储器采样数据的方法和装置
公开(公告)号：US5860128A
公开(公告)日：1999-01-12
申请号：US724370
申请日：1996-10-01
申请人： Robert N. Murdoch , Michael W. Williams , Sathyamurthi Sadhasivan
发明人： Robert N. Murdoch , Michael W. Williams , Sathyamurthi Sadhasivan
IPC分类号： G11C7/10 , G11C8/18 , G11C29/50 , G06F12/06
CPC分类号： G11C7/106 , G11C29/50 , G11C7/1024 , G11C7/1051 , G11C7/1078 , G11C8/18 , G11C11/401
摘要： A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.
摘要翻译：一种用于执行存储器访问的新方法。列地址选通（CAS）信号的下降沿用于使动态随机存取存储器（DRAM）将与当前地址相对应的数据驱动到耦合到一组锁存器的输入的数据总线上。存储器锁存数据（MLAD）信号用于使能该组锁存器。当MLAD信号被置位时，锁存器响应于CAS信号的下降沿在输入端锁存数据。当MLAD信号无效时，锁存器不会响应CAS信号的下降沿在输入端锁存数据。由于使用相同的信号（CAS）来控制数据由DRAM驱动，并且当数据被锁存器锁存时，避免了输出定时，信号路径延迟和负载的差异。因此避免了使用昂贵的定时补偿电路和对每个电路板进行重新设计的这些电路的特殊调谐。

2. 发明申请

US20100027790A1 METHODS FOR AUTHENTICATING A HARDWARE DEVICE AND PROVIDING A SECURE CHANNEL TO DELIVER DATA 审中-公开
标题翻译：用于认证硬件设备并提供安全通道以提供数据的方法
公开(公告)号：US20100027790A1
公开(公告)日：2010-02-04
申请号：US11961848
申请日：2007-12-20
申请人： Balaji Vembu , Gary Graunke , Sathyamurthi Sadhasivan , Aditya Sreenivas
发明人： Balaji Vembu , Gary Graunke , Sathyamurthi Sadhasivan , Aditya Sreenivas
IPC分类号： H04N7/167 , H04L9/08
CPC分类号： G06F21/606
摘要： A method for delivering audio/video data through a hardware device using a software application comprises, at the hardware end, receiving an encrypted application key, an encrypted random session key, and encrypted audio/video data from the software. The hardware then decrypts the encrypted application key using a secret encryption key, decrypts the encrypted random session key using the application key, and decrypts the encrypted audio/video data using the random session key. The hardware may then deliver the unencrypted audio/video data by way of a display and speakers. The secret encryption key is securely embedded within the hardware device at an earlier point in time.
摘要翻译：通过使用软件应用的硬件设备来传送音频/视频数据的方法包括在硬件端从软件接收加密的应用密钥，加密的随机会话密钥和加密的音频/视频数据。然后硬件使用秘密加密密钥解密加密的应用密钥，使用应用密钥对加密的随机会话密钥进行解密，并使用随机会话密钥解密加密的音频/视频数据。然后硬件可以通过显示器和扬声器传递未加密的音频/视频数据。秘密加密密钥在较早的时间点安全地嵌入硬件设备内。

3. 发明申请

US20090172331A1 Securing content for playback 审中-公开
标题翻译：保护播放内容
公开(公告)号：US20090172331A1
公开(公告)日：2009-07-02
申请号：US12006282
申请日：2007-12-31
申请人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
发明人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
IPC分类号： G06F21/00
CPC分类号： G06F21/84 , G06F21/10 , G06F21/74
摘要： A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may access the encrypted material, decrypt the material, and provide it to the renderer engine of a graphics engine. The graphics engine may then process the decrypted material using the protected portion of the memory. Only graphics devices can access the protected portion of the memory in at least one mode, preventing access by outside sources. In addition, the protected memory may be stolen memory that is not identified to the operating system, making that stolen memory inaccessible to applications running on the operating system.
摘要翻译：图形引擎可以包括全部连接到显示器的解密设备，渲染器和子画面或覆盖引擎。在一个实施例中，存储器可以具有受保护和非保护部分。应用可以将加密的内容存储在所述存储器的非保护部分上。解密设备可以访问加密的材料，解密材料，并将其提供给图形引擎的渲染器引擎。然后，图形引擎可以使用存储器的受保护部分来处理解密的材料。只有图形设备才能以至少一种模式访问存储器的受保护部分，从而防止外部源的访问。此外，受保护的存储器可能是未被识别到操作系统的被盗存储器，使得被盗的存储器不能在操作系统上运行的应用程序访问。

4. 发明授权

US07348957B2 Real-time dynamic design of liquid crystal display (LCD) panel power management through brightness control 有权
标题翻译：实时动态设计液晶显示（LCD）面板电源管理通过亮度控制
公开(公告)号：US07348957B2
公开(公告)日：2008-03-25
申请号：US10367070
申请日：2003-02-14
申请人： Ying Cui , Richard W. Jensen , David Wyatt , Venu M. Kuchibhotla , Sathyamurthi Sadhasivan , Todd M. Witter
发明人： Ying Cui , Richard W. Jensen , David Wyatt , Venu M. Kuchibhotla , Sathyamurthi Sadhasivan , Todd M. Witter
IPC分类号： G09G3/28
CPC分类号： G09G3/3406 , G09G3/28 , G09G2320/0626 , G09G2320/064 , G09G2320/0646 , G09G2320/0666 , G09G2320/0673 , G09G2330/021 , G09G2360/144 , G09G2360/145 , G09G2360/16
摘要： According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image data corresponding to the determined segment mode; accumulating a value of the selected portion of the received image data; comparing the accumulated value to a threshold value; and generating an interrupt signal if the accumulated value exceeds the threshold value.
摘要翻译：根据本发明的一个实施例，公开了一种用于平板显示器的电源管理方法。该方法包括：接收图像数据; 确定所接收的图像数据的分段模式; 选择与所确定的段模式相对应的所接收的图像数据的一部分; 累积接收到的图像数据的所选部分的值; 将累积值与阈值进行比较; 以及如果所述累加值超过所述阈值则产生中断信号。

5. 发明授权

US5664122A Method and apparatus for sequencing buffers for fast transfer of data between buses 失效
标题翻译：用于排序缓冲器的方法和装置，用于在总线之间快速传输数据
公开(公告)号：US5664122A
公开(公告)日：1997-09-02
申请号：US619092
申请日：1996-03-20
申请人： Jeffrey L. Rabe , Sathyamurthi Sadhasivan
发明人： Jeffrey L. Rabe , Sathyamurthi Sadhasivan
IPC分类号： G06F13/40 , G06F12/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： A buffer circuit for transferring data between a first slower narrower computer bus and a second wider faster computer bus which buffer circuit includes first and second buffers each capable of storing a plurality of bytes of data equivalent to the width of the second bus, a single address register for holding an address which represents data in either of the two buffers, the lowest order bit of the address register indicating to which one of the two buffers data is being written, first and second registers for storing indications of valid data in the first and second buffers, and a control circuit for controlling the filling of the first and the second buffers in accordance with the byte addresses furnished and the flushing of the first and the second buffers whenever a most significant byte of a buffer has valid data, whenever an attempt is made to write to a buffer address containing valid data, and whenever an attempt is made to load data to a buffer address different than an address in the address register so that sequences of bytes of data are typically accumulated in order in one buffer until an amount of data equal to that which may be transferred on the second wider faster bus is accumulated and then that buffer is flushed to the second wider faster bus while the other buffer is loaded with new data, and so that valid data is not overwritten even though non-sequential addresses are loaded.
摘要翻译：一种缓冲电路，用于在第一较窄较窄的计算机总线和第二更宽的计算机总线之间传送数据，该缓冲电路包括第一和第二缓冲器，每个缓冲器能够存储等同于第二总线的宽度的多个字节数据，单个地址注册用于保存表示两个缓冲器中的任一个中的数据的地址，地址寄存器的低位位指示正在写入两个缓冲器数据中的哪一个;第一和第二寄存器，用于存储第一和第二缓冲器数据中的有效数据的指示; 第二缓冲器，以及控制电路，用于当缓冲器的最高有效字节具有有效数据时，根据提供的字节地址和第一和第二缓冲器的刷新来控制第一和第二缓冲器的填充，被写入包含有效数据的缓冲地址，并且每当尝试将数据加载到不同于addre的缓冲地址 ss在地址寄存器中，使得数据字节序列通常在一个缓冲器中按顺序累积，直到数据量等于在第二较宽更快的总线上传送的数据量被累积，然后该缓冲器被刷新到第二个较宽的更快的总线，而另一个缓冲区加载新的数据，并且即使加载非顺序地址，有效数据也不会被覆盖。

6. 发明授权

US09589159B2 Creating secure communication channels between processing elements 有权
标题翻译：在处理元素之间创建安全的通信通道
公开(公告)号：US09589159B2
公开(公告)日：2017-03-07
申请号：US12492513
申请日：2009-06-26
申请人： Balaji Vembu , Aditya Navale , Sathyamurthi Sadhasivan
发明人： Balaji Vembu , Aditya Navale , Sathyamurthi Sadhasivan
IPC分类号： G06F12/14 , G06F21/84 , G06F21/72 , H04L9/08
CPC分类号： G06F21/84 , G06F21/72 , H04L9/0841 , H04L2209/60
摘要： Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one processing element. A first processing element, such as a bridge, may use its cryptographic functionality to request a key exchange with a second processing element, such as a graphics engine. Each processing element may include a global key which is common to the two processing elements and a unique key which is unique to each processing element. A key exchange may be established during the boot process the first time the system boots and, failing any hardware change, the same key may be used throughout the lifetime of the two processing elements. Once a secure channel is set up, any application wishing to authenticate a processing element without public-private cryptographic function may perform the authentication with the other processing element which shares a secure channel with the first processing element.
摘要翻译：单个平台中的两个处理元件可以安全通信，以允许平台在一个处理元件中利用某些加密功能。诸如桥接器的第一处理元件可以使用其加密功能来请求与诸如图形引擎的第二处理元件的密钥交换。每个处理元件可以包括两个处理元件共有的全局密钥和每个处理元件唯一的唯一密钥。在系统引导的第一次引导过程中可以建立密钥交换，并且在任何硬件改变失败的情况下，在两个处理元件的整个寿命期间可以使用相同的密钥。一旦建立了安全通道，希望在没有公共 - 私人密码功能的情况下认证处理元件的任何应用程序可以与与第一处理元件共享安全通道的其他处理元件执行认证。

7. 发明申请

US20100332852A1 Creating Secure Communication Channels Between Processing Elements 有权
标题翻译：在处理元素之间创建安全通信通道
公开(公告)号：US20100332852A1
公开(公告)日：2010-12-30
申请号：US12492513
申请日：2009-06-26
申请人： Balaji Vembu , Aditya Navale , Sathyamurthi Sadhasivan
发明人： Balaji Vembu , Aditya Navale , Sathyamurthi Sadhasivan
IPC分类号： G06F12/14 , G06F21/00 , H04L9/08
CPC分类号： G06F21/84 , G06F21/72 , H04L9/0841 , H04L2209/60
摘要： Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one processing element. A first processing element, such as a bridge, may use its cryptographic functionality to request a key exchange with a second processing element, such as a graphics engine. Each processing element may include a global key which is common to the two processing elements and a unique key which is unique to each processing element. A key exchange may be established during the boot process the first time the system boots and, failing any hardware change, the same key may be used throughout the lifetime of the two processing elements. Once a secure channel is set up, any application wishing to authenticate a processing element without public-private cryptographic function may perform the authentication with the other processing element which shares a secure channel with the first processing element.
摘要翻译：单个平台中的两个处理元件可以安全通信，以允许平台在一个处理元件中利用某些加密功能。诸如桥接器的第一处理元件可以使用其加密功能来请求与诸如图形引擎的第二处理元件的密钥交换。每个处理元件可以包括两个处理元件共有的全局密钥和每个处理元件唯一的唯一密钥。在系统引导的第一次引导过程中可以建立密钥交换，并且在任何硬件改变失败的情况下，在两个处理元件的整个寿命期间可以使用相同的密钥。一旦建立了安全通道，希望在没有公共 - 私人密码功能的情况下认证处理元件的任何应用程序可以与与第一处理元件共享安全通道的其他处理元件执行认证。

8. 发明授权

US5794070A Method and apparatus for fast DMA transfer on an industry standard architecture (ISA) bus 失效
标题翻译：用于工业标准架构（ISA）总线上快速DMA传输的方法和装置
公开(公告)号：US5794070A
公开(公告)日：1998-08-11
申请号：US730777
申请日：1996-10-16
申请人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
发明人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
摘要翻译：计算机系统包括直接存储器访问（DMA）传送单元和通过外部总线耦合的多个DMA设备。 DMA传送单元为多个DMA设备实现DMA传输。 DMA传输单元包含DMA控制器，总线仲裁器和总线控制器。 DMA控制器和总线控制器产生一个两个时钟周期的DMA传输。为了实现双时钟周期DMA传输，请求的DMA设备与DMA控制器建立DMA传输，使得在第一时钟周期期间断言DACK＃信号。在第二个时钟周期内，DMA控制器设置存储器地址。在第三个时钟周期内，总线控制器转换外部总线上的命令信号。在断言命令信号时，有效数据在外部总线上被断言。对于需求和块模式操作，在两个时钟周期的DMA传输中执行额外的DMA传输。 DMA控制器和总线控制器也产生三个时钟周期的DMA传输。

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