专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06376319B2 Process to fabricate a source-drain extension 失效
标题翻译：制造源极 - 漏极扩展的过程
公开(公告)号：US06376319B2
公开(公告)日：2002-04-23
申请号：US09972629
申请日：2001-10-09
申请人： Ting Cheong Ang , Shyue Fong Quek , Jun Song , Xing Yu
发明人： Ting Cheong Ang , Shyue Fong Quek , Jun Song , Xing Yu
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.
摘要翻译：已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

2. 发明授权

US06455384B2 Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers 有权
标题翻译：用于形成具有位于L形间隔物下方的源极/漏极延伸区域的MOSFET器件的方法
公开(公告)号：US06455384B2
公开(公告)日：2002-09-24
申请号：US09972645
申请日：2001-10-09
申请人： Ting Cheong Ang , Shyue Fong Quek , Jun Song , Xing Yu
发明人： Ting Cheong Ang , Shyue Fong Quek , Jun Song , Xing Yu
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.
摘要翻译：已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

3. 发明授权

US06090691A Method for forming a raised source and drain without using selective epitaxial growth 有权
标题翻译：在不使用选择性外延生长的情况下形成升高的源极和漏极的方法
公开(公告)号：US06090691A
公开(公告)日：2000-07-18
申请号：US439366
申请日：1999-11-15
申请人： Ting Cheong Ang , Shyue Fong Quek , Xing Yu , Ying Keung Leung
发明人： Ting Cheong Ang , Shyue Fong Quek , Xing Yu , Ying Keung Leung
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8238 , H01L29/417 , H01L21/22
CPC分类号： H01L29/66492 , H01L21/823814 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L21/2255 , H01L29/665
摘要： A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.
摘要翻译：一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。

4. 发明授权

US06611024B2 Method of forming PID protection diode for SOI wafer 有权
公开(公告)号：US06611024B2
公开(公告)日：2003-08-26
申请号：US09946981
申请日：2001-09-06
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203
摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

5. 发明授权

US06963113B2 Method of body contact for SOI MOSFET 有权
标题翻译： SOI MOSFET的体接触方法
公开(公告)号：US06963113B2
公开(公告)日：2005-11-08
申请号：US10915670
申请日：2004-08-10
申请人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
发明人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.
摘要翻译：描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。第一和第二沟槽填充有绝缘层。栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。沉积覆盖栅电极的层间电介质层。第一触点通过层间介质层开放到下面的源极和漏极区域。在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

6. 发明授权

US06582856B1 Simplified method of fabricating a rim phase shift mask 失效
标题翻译：制造轮辋相移掩模的简化方法
公开(公告)号：US06582856B1
公开(公告)日：2003-06-24
申请号：US09513872
申请日：2000-02-28
申请人： Shyue Fong Quek , Ting Cheong Ang , Jun Song , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Jun Song , Sang Yee Loong
IPC分类号： G03F900
CPC分类号： G03F1/29
摘要： A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.
摘要翻译：实现了制作边缘相移掩模的新方法。在透明基底上方设置不透明层。将抗蚀剂层沉积在不透明层上。抗蚀剂层被图案化。蚀刻不透明层和透明基板。抗蚀剂层掩盖该蚀刻。在该蚀刻期间蚀刻不透明层。因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。在相移层实施例中也可以使用蚀刻停止层。

7. 发明授权

US06275089B1 Low voltage controllable transient trigger network for ESD protection 有权
标题翻译：低电压可控瞬态触发网络，用于ESD保护
公开(公告)号：US06275089B1
公开(公告)日：2001-08-14
申请号：US09482048
申请日：2000-01-13
申请人： Jun Song , Ting Cheong Ang , Shyue Fong Quek , Lap Chan
发明人： Jun Song , Ting Cheong Ang , Shyue Fong Quek , Lap Chan
IPC分类号： H03K508
CPC分类号： H01L27/0251
摘要： A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.
摘要翻译：描述了为IC的内部电路提供静电放电（ESD）保护的瞬态保护电路。瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式，从而将ESD脉冲的幅度减小到电路的其余部分。电阻性装置与齐纳二极管并联，以在非ESD电压下提供信号路径。为了有助于将ESD电流从内部电路分流，PMOS和NMOS晶体管并联连接在正电压和负电源之间，它们的结连接到内部电路。负ESD脉冲导致PMOS晶体管导通，将ESD能量转储到正电压源中，而正的ESD脉冲使NMOS晶体管导通，将ESD能量转储到负电源。由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通，以提供大量的ESD保护。

8. 发明授权

US06258677B1 Method of fabricating wedge isolation transistors 失效
标题翻译：楔形隔离晶体管的制造方法
公开(公告)号：US06258677B1
公开(公告)日：2001-07-10
申请号：US09409875
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/76264 , H01L21/76278 , H01L21/76283 , H01L21/823878 , H01L29/41783 , H01L29/66545 , H01L29/66628 , H01L29/66651
摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.
摘要翻译：一种制造晶体管的方法，包括以下步骤。提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。在活性区域上生长外延硅以形成SEG区域。在SEG区域上形成一个虚拟门。凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。去除虚拟栅极，暴露凸起的外延硅层的内侧壁。在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间。在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间形成栅极导体。去除侧壁间隔物。不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

9. 发明授权

US06787422B2 Method of body contact for SOI mosfet 有权
标题翻译： SOI mosfet的身体接触方法
公开(公告)号：US06787422B2
公开(公告)日：2004-09-07
申请号：US09755572
申请日：2001-01-08
申请人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
发明人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.
摘要翻译：描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。第一和第二沟槽填充有绝缘层。栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。沉积覆盖栅电极的层间电介质层。第一触点通过层间介质层开放到下面的源极和漏极区域。在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

10. 发明授权

US06329253B1 Thick oxide MOS device used in ESD protection circuit 有权
标题翻译： ESD保护电路中使用的厚氧化物MOS器件
公开(公告)号：US06329253B1
公开(公告)日：2001-12-11
申请号：US09434922
申请日：1999-11-05
申请人： Jun Song , Yonqzang Zhang , Shyue Fong Quek , Ting Cheong Ang , Jun Cai , Puay Ing Ong
发明人： Jun Song , Yonqzang Zhang , Shyue Fong Quek , Ting Cheong Ang , Jun Cai , Puay Ing Ong
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L21/76224 , H01L27/0266 , H01L29/7834
摘要： A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps. This completes formation of an electrostatic discharge device in the fabrication of integrated circuits.
摘要翻译：描述了使用浅沟槽隔离技术形成新的厚氧化物静电放电装置的方法。将沟槽蚀刻到半导体衬底中。沉积在半导体衬底上并填充沟槽的氧化物层。部分地蚀刻沟槽内的氧化物，留下沟槽的侧壁和底部上的氧化物。氧化物被抛光到半导体衬底的表面，由此氧化物仅保留在沟槽的侧壁和底部上。在沟槽内形成栅极，由此栅极被氧化物包围。将第一离子注入到与沟槽相邻的半导体衬底中以形成N阱。在N阱的顶部将第二离子注入到半导体衬底中以形成源/漏区。将第三离子注入位于N阱下方并位于沟槽下方的半导体衬底中以形成静电放电触发抽头。这就形成了集成电路制造中的静电放电装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式