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    • 1. 发明授权
    • Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug
    • 带有非绝缘缺口栅极盖层的引出源极漏极漏极,漏极侧壁钝化并填充有电介质插塞
    • US07700425B2
    • 2010-04-20
    • US11585361
    • 2006-10-23
    • Tina J. WagnerWerner A. RauschSadanand V. Deshpande
    • Tina J. WagnerWerner A. RauschSadanand V. Deshpande
    • H01L21/8238
    • H01L29/66772H01L29/78618
    • A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.
    • 提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法,在栅电极堆叠的侧壁上具有侧壁间隔物,并且形成在硅层的表面上的升高的源极/漏极区域。 栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。 通过将掺杂剂注入到其表面中,在栅电极的顶表面中形成薄的非晶硅覆盖层。 凹口蚀刻到盖层的周边。 在凹口中形成介电材料塞。 栅电极的侧壁被覆盖一部分插塞的侧壁间隔物覆盖,以消除栅极多晶硅的暴露,从而避免在形成升高的源极/漏极区域期间形成假外延生长。