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1. 发明授权

US06387790B1 Conversion of amorphous layer produced during IMP Ti deposition 有权
标题翻译：在IMP Ti沉积期间产生的非晶层的转化
公开(公告)号：US06387790B1
公开(公告)日：2002-05-14
申请号：US09602228
申请日：2000-06-23
申请人： Anthony Gene Domenicucci , Chung-Ping Eng , William Joseph Murphy , Tina J. Wagner , Yun-Yu Wang , Kwong Hon Wong
发明人： Anthony Gene Domenicucci , Chung-Ping Eng , William Joseph Murphy , Tina J. Wagner , Yun-Yu Wang , Kwong Hon Wong
IPC分类号： H01L213205
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76864
摘要： A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma deposited Ti into a substantially crystalline region includes (a) providing a structure having at least one contact hole formed therein, said at least one contact hole exposing at least a portion of a cobalt disilicide contact formed in a semiconductor substrate; (b) depositing a Ti/TiN liner in said at least one contact hole by ionized metal plasma deposition; (c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region including a TiSi2 top layer and a CoSix bottom layer; and (d) optionally forming a conductive material on said Ti/TiN liner.
摘要翻译：提供一种制造具有良好接触电阻和接触孔覆盖度的含Ti衬垫的方法。将电离金属等离子体沉积的Ti的非晶区域转化成基本上结晶的区域的方法包括（a）提供其中形成有至少一个接触孔的结构，所述至少一个接触孔暴露至少一部分二硅化钴接触形成在半导体衬底中; （b）通过电离金属等离子体沉积在所述至少一个接触孔中沉积Ti / TiN衬垫; （c）在有效使所述退火过程中形成的任何非晶区域再结晶成包括TiSi 2顶层和CoSix底层的结晶区域的条件下退火所述Ti / TiN衬垫; 和（d）任选地在所述Ti / TiN衬垫上形成导电材料。

2. 发明授权

US5811357A Process of etching an oxide layer 失效
标题翻译：蚀刻氧化层的工艺
公开(公告)号：US5811357A
公开(公告)日：1998-09-22
申请号：US824744
申请日：1997-03-26
申请人： Michael D. Armacost , Tina J. Wagner , Michael L. Passow , Dominic J. Schepis , Matthew J. Sendelbach , William C. Wille
发明人： Michael D. Armacost , Tina J. Wagner , Michael L. Passow , Dominic J. Schepis , Matthew J. Sendelbach , William C. Wille
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116
摘要： A dry etching process for etching an oxide layer on a substrate in which a plasma is created in a gaseous mixture containing C.sub.4 F.sub.8 and C.sub.2 F.sub.6. The dry etch process is useful for etching an oxide layer stopping on a silicon nitride layer on a semiconductor wafer of an integrated circuit structure as it eliminates resist blistering without sacrificing high selectivity to nitride, via wall angle, and/or etch uniformity.
摘要翻译：用于蚀刻在其中在含有C 4 F 8和C 2 F 6的气体混合物中产生等离子体的衬底上的氧化物层的干蚀刻工艺。干蚀刻工艺对于蚀刻在集成电路结构的半导体晶片上的氮化硅层上停止的氧化物层是有用的，因为它消除了抗蚀剂起泡，而不牺牲对氮化物，经由壁角度和/或蚀刻均匀性的高选择性。

3. 发明授权

US07700425B2 Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug 失效
标题翻译：带有非绝缘缺口栅极盖层的引出源极漏极漏极，漏极侧壁钝化并填充有电介质插塞
公开(公告)号：US07700425B2
公开(公告)日：2010-04-20
申请号：US11585361
申请日：2006-10-23
申请人： Tina J. Wagner , Werner A. Rausch , Sadanand V. Deshpande
发明人： Tina J. Wagner , Werner A. Rausch , Sadanand V. Deshpande
IPC分类号： H01L21/8238
CPC分类号： H01L29/66772 , H01L29/78618
摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.
摘要翻译：提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。通过将掺杂剂注入到其表面中，在栅电极的顶表面中形成薄的非晶硅覆盖层。凹口蚀刻到盖层的周边。在凹口中形成介电材料塞。栅电极的侧壁被覆盖一部分插塞的侧壁间隔物覆盖，以消除栅极多晶硅的暴露，从而避免在形成升高的源极/漏极区域期间形成假外延生长。

4. 发明授权

US06930030B2 Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness 失效
标题翻译：在硅的薄膜的表面上的凹部上形成电子器件的方法被蚀刻到精确的厚度
公开(公告)号：US06930030B2
公开(公告)日：2005-08-16
申请号：US10453080
申请日：2003-06-03
申请人： Werner A. Rausch , Tina J. Wagner , Sadanand V. Deshpande
发明人： Werner A. Rausch , Tina J. Wagner , Sadanand V. Deshpande
IPC分类号： H01L21/265 , H01L21/28 , H01L21/3065 , H01L21/3213 , H01L21/336 , H01L29/78 , H01L21/3205 , H01L21/302
CPC分类号： H01L29/66621 , H01L21/26506 , H01L21/2658 , H01L21/28114 , H01L21/3065 , H01L21/32137 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/7834
摘要： A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask. In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.
摘要翻译：用于精确稀化以在晶体硅层中形成精确深度的凹槽的方法，其可用于形成诸如MOSFET器件的各种器件，包括以下步骤。在硅层的顶表面上形成具有窗口的图案掩模。在窗口下方的硅层的顶表面形成非晶化区域。选择性地蚀刻去除硅层的非晶化区域，以在硅层表面形成凹陷，并去除图形掩模。在MOSFET器件的情况下，在图案掩模下形成硬掩模，窗口延伸穿过其中。然后通过硬掩模在窗口中产生侧壁间隔物，并在窗口中形成栅极电极堆叠。然后去除硬掩模，形成源极/漏极延伸部分，光晕和区域加上硅化物，并完成MOSFET器件。

5. 发明授权

US06878624B1 Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi 失效
标题翻译： CoSi的预退火，以防止在Ti-O-N和CoSi之间形成非晶层
公开(公告)号：US06878624B1
公开(公告)日：2005-04-12
申请号：US10674645
申请日：2003-09-30
申请人： John Bruley , Cyril Cabral, Jr. , Christian Lavoie , Tina J. Wagner , Yun Yu Wang , Horati S. Wildman , Wong Kwong Hon
发明人： John Bruley , Cyril Cabral, Jr. , Christian Lavoie , Tina J. Wagner , Yun Yu Wang , Horati S. Wildman , Wong Kwong Hon
IPC分类号： H01L21/336 , H01L21/44 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76855 , H01L21/76856 , H01L29/665
摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.
摘要翻译：本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

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