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    • 3. 发明授权
    • Multiplexer for a TX/RX capacitance sensing panel
    • 用于TX / RX电容检测面板的多路复用器
    • US09377905B1
    • 2016-06-28
    • US13360296
    • 2012-01-27
    • Edward GrivnaTimothy WilliamsHans Klein
    • Edward GrivnaTimothy WilliamsHans Klein
    • G06F3/044G06F3/041
    • G06F3/044G06F3/0416G06F2203/04111
    • An embodiment of a multiplexer circuit may include a plurality of PTOTAL receive (RX) channel outputs and a plurality of QTOTAL pins, where QTOTAL is greater than PTOTAL. Each of a first subset and a third subset of the plurality of QTOTAL pins may be switchably coupled to at least one of the plurality of RX channels, each of a second subset of the plurality of QTOTAL pins is switchably coupled to two of the plurality of RX channels, and for each possible subset of PTOTAL contiguous pins from the plurality of QTOTAL pins, each pin in the possible subset may be switchably coupled to a different RX channel output of the plurality of RX channel outputs.
    • 多路复用器电路的实施例可以包括多个PTOTAL接收(RX)信道输出和多个QTOTAL引脚,其中QTOTAL大于PTOTAL。 多个QTOTAL引脚的第一子集和第三子集中的每一个可以可切换地耦合到多个RX信道中的至少一个,多个QTOTAL引脚的第二子集中的每一个可切换地耦合到多个 RX通道,并且对于来自多个QTOTAL引脚的PTOTAL连续引脚的每个可能子集,可能子集中的每个引脚可以可切换地耦合到多个RX通道输出的不同RX通道输出。
    • 6. 发明申请
    • ORTHOGONAL REGISTER ACCESS
    • 正交寄存器访问
    • US20080263328A1
    • 2008-10-23
    • US11859547
    • 2007-09-21
    • Timothy WilliamsGregory John VergeDennis Seguine
    • Timothy WilliamsGregory John VergeDennis Seguine
    • G06F9/38
    • G06F7/785
    • Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or in an orthogonal fashion corresponding to the selected column. Thus, when a particular row is selected, a register operation may be carried out for each bit of the selected row to produce a parallel register output, such as by reading/writing each bit of the selected row to a parallel register. On the other hand, when a particular column is selected, a register operation may be carried out for each bit of the selected column, such as by reading/writing each bit of the selected column to an orthogonal register. The orthogonal register access allows for fast and efficient access to a particular bit in the set of parallel registers.
    • 本发明的实施例涉及一种用于正交地访问一组并行寄存器的方法和系统。 解码器可以用于选择并行寄存器集合的特定行或列,以对应于所选行的并行方式或对应于所选列的正交方式执行寄存器操作。 因此,当选择特定行时,可以对所选择的行的每个位执行寄存器操作以产生并行寄存器输出,例如通过将所选择的行的每个位读/写到并行寄存器。 另一方面,当选择特定列时,可以对所选列的每个位执行寄存器操作,例如通过将所选列的每个位读/写为正交寄存器。 正交寄存器访问允许快速和有效地访问该并行寄存器集合中的特定位。
    • 10. 发明授权
    • State-monitoring memory element
    • 状态监视记忆元素
    • US08462576B2
    • 2013-06-11
    • US13303112
    • 2011-11-22
    • Michael SheetsTimothy Williams
    • Michael SheetsTimothy Williams
    • G11C5/14
    • G11C5/14H03K19/17764
    • Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage.
    • 本发明的实施例涉及一种状态监视存储元件。 状态监视存储元件可以通过在二极管和/或晶体管上降低对状态监视存储元件的输入电压供应来实现。 可以使用一个或多个电流源来压力状态监视存储元件。 可以使用逻辑分析器来分析状态监视存储器元件的完整性,并且响应于检测状态监视存储器元件中的故障而触发IC中的适当动作,例如复位,停止,移除电力,中断。 多个状态监视存储器元件可能在IC上的不同位置被干扰以获得​​更好的覆盖。