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1. 发明授权

US06908816B1 Method for forming a dielectric spacer in a non-volatile memory device 有权
标题翻译：在非易失性存储器件中形成电介质间隔物的方法
公开(公告)号：US06908816B1
公开(公告)日：2005-06-21
申请号：US10696234
申请日：2003-10-28
申请人： Timothy Thurgate , Nga-Ching Wong
发明人： Timothy Thurgate , Nga-Ching Wong
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/6656
摘要： Embodiments of the present invention relate to a method for fabricating a Vss line in a memory device, which comprises: forming a plurality of memory cells above a semiconductor substrate, forming a channel between two of the memory cells, forming an oxide/nitride/oxide stack above the memory cells and the channel, removing a portion of the oxide/nitride/oxide stack between the memory cells to expose the semiconductor substrate, removing the oxide/nitride/oxide stack above the gates of the memory cells, forming a plurality of source regions in the substrate between the memory cells, forming a poly-silicon layer above the memory cells and the channel to connect to the source regions, and removing a sufficient portion of the poly-silicon layer to form a Vss line.
摘要翻译：本发明的实施例涉及一种用于在存储器件中制造Vss线的方法，包括：在半导体衬底上形成多个存储单元，在两个存储单元之间形成通道，形成氧化物/氮化物/氧化物堆叠在存储器单元和通道上方，去除存储单元之间的氧化物/氮化物/氧化物堆叠的一部分以暴露半导体衬底，去除存储器单元的栅极之上的氧化物/氮化物/氧化物堆叠，形成多个在存储单元之间的衬底中的源极区域，在存储器单元上方形成多晶硅层和连接到源极区域的沟道，以及去除足够部分的多晶硅层以形成Vss线。

2. 发明授权

US07067381B1 Structure and method to reduce drain induced barrier lowering 有权
标题翻译：减少漏极引起的屏障降低的结构和方法
公开(公告)号：US07067381B1
公开(公告)日：2006-06-27
申请号：US10636336
申请日：2003-08-06
申请人： Timothy Thurgate , Nga-Ching Wong
发明人： Timothy Thurgate , Nga-Ching Wong
IPC分类号： H01L21/331
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： Embodiments of the present invention include a method for manufacturing a transistor comprising forming a gate conductor above a semiconductor substrate; forming a lightly doped implant region within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and forming a counter doping implant region within the substrate, wherein the counter-doping implant region is substantially on the drain side and wherein the counter-doping reduces the net channel impurity concentration on the drain side.
摘要翻译：本发明的实施例包括一种用于制造晶体管的方法，包括在半导体衬底上形成栅极导体; 在所述衬底内形成轻掺杂的注入区域，其中所述轻掺杂注入区域基本上位于所述晶体管的源极侧; 以及在所述衬底内形成反掺杂注入区，其中所述反掺杂注入区基本上在所述漏极侧，并且其中所述反掺杂减少所述漏极侧的净沟道杂质浓度。

3. 发明授权

US07049188B2 Lateral doped channel 有权
标题翻译：横向掺杂通道
公开(公告)号：US07049188B2
公开(公告)日：2006-05-23
申请号：US10305724
申请日：2002-11-26
申请人： Nga-Ching Wong , Timothy Thurgate , Sameer S. Haddad
发明人： Nga-Ching Wong , Timothy Thurgate , Sameer S. Haddad
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/1045 , H01L29/66825 , H01L29/66833
摘要： A lateral doped channel. A first doping material is implanted substantially vertically into a region adjacent to a gate structure. A diffusion process diffuses the first doping material into a channel region beneath the gate structure. A second doping material is implanted substantially vertically into the region adjacent to a gate structure. The second implantation forms source/drain regions and may terminate the channel region. The channel region thus comprises a laterally non-uniform doping profile which beneficially mitigates the short channel effect and is highly advantageous as compensation for manufacturing process variations in channel length.
摘要翻译：横向掺杂通道。第一掺杂材料基本上垂直地植入到与栅极结构相邻的区域中。扩散过程将第一掺杂材料扩散到栅极结构下方的沟道区域中。基本垂直地将第二掺杂材料注入到与栅极结构相邻的区域中。第二注入形成源极/漏极区域并且可以终止沟道区域。因此，通道区域包括横向不均匀的掺杂分布，其有利地减轻了短沟道效应，并且作为对通道长度的制造工艺变化的补偿是非常有利的。

4. 发明授权

US07208382B1 Semiconductor device with high conductivity region using shallow trench 有权
标题翻译：具有高导电性的半导体器件采用浅沟槽
公开(公告)号：US07208382B1
公开(公告)日：2007-04-24
申请号：US10151595
申请日：2002-05-16
申请人： Jeffrey P. Erhardt , Kashmir S. Sahota , Emmanuil Lingunis , Nga-Ching Wong
发明人： Jeffrey P. Erhardt , Kashmir S. Sahota , Emmanuil Lingunis , Nga-Ching Wong
IPC分类号： H01L21/04
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66621 , H01L29/66636
摘要： A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.
摘要翻译：提供了一种具有其中设置有开口的半导体衬底的集成电路的方法和结构。掺杂的高导电性区域由开口中的掺杂材料和靠近开口中的掺杂材料的扩散掺杂区形成。结构在从由字线，栅极，电介质层及其组合组成的组中选择的掺杂高导电率区域之上。

5. 发明授权

US06475816B1 Method for measuring source and drain junction depth in silicon on insulator technology 失效
标题翻译：硅绝缘体技术测量源极和漏极结深度的方法
公开(公告)号：US06475816B1
公开(公告)日：2002-11-05
申请号：US09781435
申请日：2001-02-13
申请人： Concetta Riccobene , Nga-Ching Wong , Tim Thurgate
发明人： Concetta Riccobene , Nga-Ching Wong , Tim Thurgate
IPC分类号： H01L2166
CPC分类号： H01L22/14 , G01R31/27
摘要： A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its “bottom transistor” formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a “reference library”. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the inspected SOI device is accurately determined by a simple electrical measurement of threshold voltage.
摘要翻译：提供了一种用于精确地确定绝缘体上硅（SOI）器件的结深度的方法。实施例包括通过测量其源极和漏极区域形成的其“底部晶体管”及其衬底作为栅极的阈值电压来确定被检查的SOI器件中的结深度。 SOI器件的底部晶体管的阈值电压以其可预测的方式随其结深度而变化。因此，通过将其底部晶体管阈值电压与已知结深度的相应参考SOI器件的底部晶体管阈值电压进行比较来确定被检查器件的结深度以找到匹配。例如，具有与被预先计算的结深度和底部晶体管阈值电压的被检查器件相同特性的模拟SOI器件被用作“参考库”。如果被检查装置的底部晶体管阈值电压具有与特定参考装置的底部晶体管阈值电压相同的值，则所检查的装置具有该特定参考装置的结深度。因此，通过阈值电压的简单电测量精确地确定被检查的SOI器件的结深度。

6. 发明授权

US07232729B1 Method for manufacturing a double bitline implant 有权
标题翻译：双位线植入物的制造方法
公开(公告)号：US07232729B1
公开(公告)日：2007-06-19
申请号：US10431321
申请日：2003-05-06
申请人： Nga-Ching Wong
发明人： Nga-Ching Wong
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/66825 , H01L29/7833
摘要： The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep more heavily doped region, disposed laterally within the shallow heavily doped region and vertically within and below the shallow heavily doped region. In an optional feature of the present invention, the method further comprises selectively implanting a second impurity, wherein the doping profile of the deep more heavily doped region is graded.
摘要翻译：本发明提供一种制造掺杂半导体区域的方法，包括选择性地注入第一杂质以形成浅重掺杂区域。该方法还包括选择性地注入第一杂质以形成深度更重的掺杂区域，其横向设置在浅重掺杂区域内并且垂直地在浅重掺杂区域内和下方。在本发明的可选特征中，该方法还包括选择性地注入第二杂质，其中深度更重掺杂区域的掺杂分布被分级。

7. 发明授权

US07151292B1 Dielectric memory cell structure with counter doped channel region 有权
标题翻译：具有反掺杂沟道区的介质存储单元结构
公开(公告)号：US07151292B1
公开(公告)日：2006-12-19
申请号：US10342549
申请日：2003-01-15
申请人： Nga-Ching Wong
发明人： Nga-Ching Wong
IPC分类号： H01L29/76
CPC分类号： H01L29/7923 , G11C16/0475 , H01L29/66833
摘要： A charge trapping dielectric memory cell array comprises a plurality of parallel bit lines implanted within the lightly doped substrate. The parallel bit lines define a plurality of channel regions spaced there between and form a semiconductor junction there with. A plurality of parallel and spaced apart word lines are positioned above the surface of the substrate and separated from the substrate by a charge trapping dielectric. The plurality of parallel word lines are perpendicularly positioned with respect to the bit lines. Each channel region comprises a central counter doped channel region adjacent to a top surface of the substrate and vertically extending into the channel region to a depth less than the bit line depth and being spaced from each semiconductor junction by a pocket region.
摘要翻译：电荷捕获介质存储单元阵列包括在轻掺杂衬底内注入的多个并行位线。并行位线限定在其间隔开的多个沟道区，并在其间形成半导体结。多个平行且间隔开的字线位于衬底的表面上方并且通过电荷俘获电介质与衬底分离。多个平行字线相对于位线垂直定位。每个沟道区域包括与衬底的顶表面相邻并且垂直延伸到沟道区的深度小于位线深度的深度的中心反相掺杂沟道区，并且通过一个凹穴区与每个半导体结隔开。

8. 发明授权

US07023740B1 Substrate bias for programming non-volatile memory 有权
标题翻译：用于编程非易失性存储器的衬底偏置
公开(公告)号：US07023740B1
公开(公告)日：2006-04-04
申请号：US10755979
申请日：2004-01-12
申请人： Nga-Ching Wong , Darlene G. Hamilton
发明人： Nga-Ching Wong , Darlene G. Hamilton
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.
摘要翻译：用于编程非易失性存储器的衬底偏置的方法和系统。在包括用于非易失性存储单元的沟道区的阱下的深阱结构中施加偏置电压。在编程期间，施加到深阱的负偏压有利地在通道区域内产生电子的不均匀分布，在通道区域的表面具有大量电子。向控制栅极和漏极施加额外的偏置电压可能导致电子从沟道区迁移到非易失性存储单元的存储层。有利地，由于在通道区域的表面处的电子供应增加，非易失性电池的编程比常规技术更快。

9. 发明申请

US20070166938A1 SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH 审中-公开
标题翻译：具有高电导率区域的半导体器件使用SHOWOW TRENCH
公开(公告)号：US20070166938A1
公开(公告)日：2007-07-19
申请号：US11685711
申请日：2007-03-13
申请人： Jeffrey Erhardt , Kashmir Sahota , Emmanuil Lingunis , Nga-Ching Wong
发明人： Jeffrey Erhardt , Kashmir Sahota , Emmanuil Lingunis , Nga-Ching Wong
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66621 , H01L29/66636
摘要： A structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.
摘要翻译：为具有设置有开口的半导体基板的集成电路提供结构。掺杂的高导电性区域由开口中的掺杂材料和靠近开口中的掺杂材料的扩散掺杂区形成。结构在从由字线，栅极，电介质层及其组合组成的组中选择的掺杂高导电率区域之上。

10. 发明申请

US20050153508A1 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
公开(公告)号：US20050153508A1
公开(公告)日：2005-07-14
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
发明人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

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