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1. 发明申请

US20080320348A1 Launch-On-Shift Support for On-Chip-Clocking 有权
标题翻译：片上时钟启动转移支持
公开(公告)号：US20080320348A1
公开(公告)日：2008-12-25
申请号：US11767606
申请日：2007-06-25
申请人： Timothy N. Ayres , Peter Wohl , John A. Waicukauski
发明人： Timothy N. Ayres , Peter Wohl , John A. Waicukauski
IPC分类号： G06F11/00
CPC分类号： G01R31/318552 , G01R31/318558 , G01R31/318594
摘要： A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the non-capture domains and the capture domains caused by asynchronous clock signals is eliminated.
摘要翻译：提出了一种用于对具有多个时钟域的集成电路执行启动扫描的方法。集成电路包括捕获时钟域和非捕获时钟域。非捕获时钟域的测试向量的部分被移入非捕获时钟域的扫描链，并允许在最后一个移位发射周期和捕获时钟域的捕获周期之前稳定。因此，消除了由异步时钟信号引起的非捕获域和捕获域之间的定时的不确定性。

2. 发明授权

US07882410B2 Launch-on-shift support for on-chip-clocking 有权
标题翻译：片上时钟启动转移支持
公开(公告)号：US07882410B2
公开(公告)日：2011-02-01
申请号：US11767606
申请日：2007-06-25
申请人： Timothy N. Ayres , Peter Wohl , John A. Waicukauski
发明人： Timothy N. Ayres , Peter Wohl , John A. Waicukauski
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318552 , G01R31/318558 , G01R31/318594
摘要： A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the non-capture domains and the capture domains caused by asynchronous clock signals is eliminated.
摘要翻译：提出了一种用于对具有多个时钟域的集成电路执行启动扫描的方法。集成电路包括捕获时钟域和非捕获时钟域。非捕获时钟域的测试向量的部分被移入非捕获时钟域的扫描链，并允许在最后一个移位发射周期和捕获时钟域的捕获周期之前稳定。因此，消除了由异步时钟信号引起的非捕获域和捕获域之间的定时的不确定性。

3. 发明授权

US08464115B2 Fully X-tolerant, very high scan compression scan test systems and techniques 有权
标题翻译：全X容忍，非常高的扫描压缩扫描测试系统和技术
公开(公告)号：US08464115B2
公开(公告)日：2013-06-11
申请号：US13172752
申请日：2011-06-29
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318547
摘要： Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
摘要翻译：扫描测试和扫描压缩是实现成本降低和出货质量的关键。更复杂设计中的新缺陷类型需要增加压缩。然而，未知（X）值的增加的密度降低了有效压缩。扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

4. 发明申请

US20110258503A1 Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques 有权
标题翻译：全X容忍，非常高的扫描压缩扫描测试系统和技术
公开(公告)号：US20110258503A1
公开(公告)日：2011-10-20
申请号：US13172752
申请日：2011-06-29
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318547
摘要： Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
摘要翻译：扫描测试和扫描压缩是实现成本降低和出货质量的关键。更复杂设计中的新缺陷类型需要增加压缩。然而，未知（X）值的增加的密度降低了有效压缩。扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

5. 发明申请

US20080256497A1 Scan compression circuit and method of design therefor 有权
标题翻译：扫描压缩电路及其设计方法
公开(公告)号：US20080256497A1
公开(公告)日：2008-10-16
申请号：US11807119
申请日：2007-05-25
申请人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
发明人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： H03M7/30 , G06F17/505 , G06F2217/14
摘要： A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
摘要翻译：基于扫描的电路包括通过多个观察逻辑实现的选择器。每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

6. 发明申请

US20080256274A1 Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit 有权
标题翻译：管道附加存储元件，用于移动组合扫描压缩电路的输入/输出数据
公开(公告)号：US20080256274A1
公开(公告)日：2008-10-16
申请号：US11786968
申请日：2007-04-13
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G06F13/38
CPC分类号： G01R31/318547
摘要： An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.
摘要翻译：电子设备包括基于扫描的电路，其包括组合式解压缩器，组合式压缩器，扫描链和通常包括多个存储元件的逻辑。通常需要通过使用位于外部接口和组合元件之一之间的一个或多个额外的存储元件来将数据移入或移出到电子设备的外部接口的扫描单元之外的周期时间（解压缩机/压缩机）。所述一个或多个附加存储元件形成流水线，其将压缩数据分阶段地跨越外部接口和组合元件之一之间的另外长的路径的小部分。分段移位导致循环时间的限制下降到穿越流水线所需的最长时间。缩短的周期时间又使移位频率相应增加。

7. 发明授权

US07958472B2 Increasing scan compression by using X-chains 有权
标题翻译：通过使用X链增加扫描压缩
公开(公告)号：US07958472B2
公开(公告)日：2011-06-07
申请号：US12242573
申请日：2008-09-30
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
IPC分类号： G06F17/50 , G06F11/22 , G01R31/28
CPC分类号： G01R31/318547
摘要： To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
摘要翻译：为了在IC设计测试期间增加扫描压缩，提供X链方法。在该方法中，识别可能捕获X的扫描单元的子集，然后将其放置在单独的X链上。可以提供卸载选择器和/或卸载压缩机的配置和观察模式。配置和观察模式为非-X链提供了大于针对X链提供的第二压缩的第一压缩。可以基于这种配置和观察模式来修改ATPG。这种X链方法可以完全集成在测试（DFT）流程中，不需要额外的用户输入，对面积和时间的影响可以忽略不计。对于具有高X密度的设计，工业设计的测试生成结果显示出显着增加的压缩率，而不损失覆盖范围。

8. 发明授权

US07237162B1 Deterministic BIST architecture tolerant of uncertain scan chain outputs 有权
标题翻译：确定性BIST架构容忍不确定的扫描链输出
公开(公告)号：US07237162B1
公开(公告)日：2007-06-26
申请号：US10263334
申请日：2002-10-01
申请人： Peter Wohl , John A. Waicukauski
发明人： Peter Wohl , John A. Waicukauski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318558
摘要： A BIST architecture that allows efficient compression and application of deterministic ATPG patterns while tolerating uncertain bits is provided. In accordance with one feature of the invention, a large number of short scan chains can be configured between a decompressor and an observe selector. The observe selector selectively presents values of specific scan chains or scan cells to an external tester, thereby significantly reducing test data and test cycles. Advantageously, the core of the tested device is not changed as would be the case in BIST architectures including MISRs. Moreover, test points or logic to block uncertain bits do not need to be inserted. Furthermore, the loaded care bits for the scan chains as well as the bits for controlling the observe selector can be deterministically controlled, thereby providing optimal testing flexibility.
摘要翻译：提供了一种允许有效压缩和应用确定性ATPG模式同时容忍不确定位的BIST架构。根据本发明的一个特征，可以在减压器和观察选择器之间配置大量的短扫描链。观察选择器选择性地将特定扫描链或扫描细胞的值呈现给外部测试仪，从而显着降低测试数据和测试周期。有利的是，测试设备的核心不会像BIST架构（包括MISR）那样发生变化。此外，不需要插入测试点或逻辑来阻止不确定位。此外，用于扫描链的加载护理位以及用于控制观察选择器的位可以被确定地控制，从而提供最佳的测试灵活性。

9. 发明授权

US06993694B1 Deterministic bist architecture including MISR filter 有权
标题翻译：确定性bist架构，包括MISR过滤器
公开(公告)号：US06993694B1
公开(公告)日：2006-01-31
申请号：US10117747
申请日：2002-04-05
申请人： Rohit Kapur , Thomas W. Williams , Tony Taylor , Peter Wohl , John A. Waicukauski
发明人： Rohit Kapur , Thomas W. Williams , Tony Taylor , Peter Wohl , John A. Waicukauski
IPC分类号： G01R31/28 , G01R31/08
CPC分类号： G01R31/318547 , G01R31/318558
摘要： A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.
摘要翻译：提供了一种用于防止测试扫描链输出的不确定位提供给MISR的滤波器。滤波器可以包括用于从扫描链接收比特的选通结构和用于如果该比特是不确定比特，则向选通结构提供预定信号的控制电路。在一个实施例中，门控结构可以包括逻辑门，诸如AND或OR门。控制电路可以包括与向扫描链提供信号的图案发生器基本相似的组件。例如，控制电路可以包括用于加载LFSR的LFSR和PRPG阴影。在一个实施例中，控制电路还可以包括用于接收来自LFSR的输入并向门控结构提供输出的移相器。

10. 发明授权

US08549372B2 ATPG and compression by using majority gates 有权
标题翻译： ATPG和通过使用多数门压缩
公开(公告)号：US08549372B2
公开(公告)日：2013-10-01
申请号：US13412575
申请日：2012-03-05
申请人： Peter Wohl , John A. Waicukauski
发明人： Peter Wohl , John A. Waicukauski
IPC分类号： G01R31/28
CPC分类号： G01R31/318357
摘要： A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.
摘要翻译：增加自动测试模式生成（ATPG）有效性和压缩的方法可以识别“多数门”的实例，并修改测试生成以利用其行为，以便需要较少的关心位。此方法可以增加测试覆盖范围并减少CPU时间，因为现在测试了以前中止的故障。多数门增强ATPG不需要硬件支持，可以应用于任何ATPG系统。

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