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1. 发明授权

US08151075B2 Multiple access type memory and method of operation 有权
标题翻译：多路访问类型的存储器和操作方法
公开(公告)号：US08151075B2
公开(公告)日：2012-04-03
申请号：US12692125
申请日：2010-01-22
申请人： Timothy J. Strauss , David W. Chrudimsky , William C. Moyer
发明人： Timothy J. Strauss , David W. Chrudimsky , William C. Moyer
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , Y02D10/13
摘要： A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.
摘要翻译：用于访问存储器的方法包括接收第一地址，其中第一地址对应于需求提取，接收第二地址，其中第二地址对应于推测预取，响应于请求提取从存储器提供第一数据，其中，第一数据被访问与系统时钟异步，并且响应于与系统时钟同步地访问第二数据的推测预取，从存储器提供第二数据。存储器可以包括多个流水线级，其中响应于需求提取而提供第一数据被执行，使得每个流水线级是独立于系统时钟的自定时的，并且响应于推测的预取来提供第二数据使得每个流水线级基于与系统时钟同步的系统时钟来定时。

2. 发明申请

US20110185146A1 MULTIPLE ACCESS TYPE MEMORY AND METHOD OF OPERATION 有权
标题翻译：多种访问类型的存储器和操作方法
公开(公告)号：US20110185146A1
公开(公告)日：2011-07-28
申请号：US12692125
申请日：2010-01-22
申请人： Timothy J. Strauss , David W. Chrudimsky , William C. Moyer
发明人： Timothy J. Strauss , David W. Chrudimsky , William C. Moyer
IPC分类号： G06F12/00 , G06F1/04
CPC分类号： G06F12/0215 , Y02D10/13
摘要： A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.
摘要翻译：用于访问存储器的方法包括接收第一地址，其中第一地址对应于需求提取，接收第二地址，其中第二地址对应于推测预取，响应于请求提取从存储器提供第一数据，其中，第一数据被访问与系统时钟异步，并且响应于与系统时钟同步地访问第二数据的推测预取，从存储器提供第二数据。存储器可以包括多个流水线级，其中响应于需求提取而提供第一数据被执行，使得每个流水线级是独立于系统时钟的自定时的，并且响应于推测的预取来提供第二数据使得每个流水线级基于与系统时钟同步的系统时钟来定时。

3. 发明授权

US09191007B1 Latching level shifter and method of operation 有权
标题翻译：锁定电平转换器及操作方法
公开(公告)号：US09191007B1
公开(公告)日：2015-11-17
申请号：US14310579
申请日：2014-06-20
申请人： Jon S. Choy , David W. Chrudimsky
发明人： Jon S. Choy , David W. Chrudimsky
IPC分类号： H03K19/0175 , H03K19/0185 , H03K3/356
CPC分类号： H03K3/356113 , H03K3/35613 , H03K19/018507 , H03K19/018521 , H03K19/018528
摘要： A latching level shifter coupled to a first power supply voltage is driven by a logic circuit coupled to a second power supply voltage. The latching level shifter is driven in a first mode to store a state based on an input signal received by the logic circuit, the first and second power supply voltages are set at first and second initial voltage levels. The latching level shifter is driven in a second mode subsequent to the first mode, the first power supply voltage is set to an intermediate voltage level. The latching level shifter is driven in a high voltage protection mode to produce an output voltage based on the state, the first power supply voltage is set to a final voltage level that is greater than a final voltage level of the second power supply voltage. The high voltage protection mode is subsequent to the second mode.
摘要翻译：耦合到第一电源电压的锁存电平移位器由耦合到第二电源电压的逻辑电路驱动。闩锁电平移位器在第一模式下被驱动以存储基于由逻辑电路接收的输入信号的状态，第一和第二电源电压被设置在第一和第二初始电压电平。锁存电平移位器在第一模式之后以第二模式被驱动，第一电源电压被设置为中间电压电平。锁存电平移位器在高电压保护模式下被驱动以产生基于状态的输出电压，第一电源电压被设置为大于第二电源电压的最终电压电平的最终电压电平。高电压保护模式在第二模式之后。

4. 发明授权

US07564716B2 Memory device with retained indicator of read reference level 有权
标题翻译：具有读参考电平保持指示的存储器
公开(公告)号：US07564716B2
公开(公告)日：2009-07-21
申请号：US11560554
申请日：2006-11-16
申请人： Ronald J. Syzdek , David W. Chrudimsky , Xiaojie He
发明人： Ronald J. Syzdek , David W. Chrudimsky , Xiaojie He
IPC分类号： G11C11/34
CPC分类号： G11C16/28
摘要： A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.
摘要翻译：为非易失性存储器阵列的一组位单元确定多个读取参考的读取参考电平。读取参考电平的指示符存储在与该位单元组相关联的非易失性存储单元中。读取参考电平的指示符是响应于对该组单元的读取访问操作而被访问的，并且基于所读取的参考电平的指示符来感测存储在该位组单元的存储单元处的值，该位单元组的存储器位置与读访问操作相关联。

5. 发明申请

US20080013384A1 Concurrent programming and program verification of floating gate transistor 有权
公开(公告)号：US20080013384A1
公开(公告)日：2008-01-17
申请号：US11487863
申请日：2006-07-17
申请人： Jon S. Choy , David W. Chrudimsky , Thomas Jew
发明人： Jon S. Choy , David W. Chrudimsky , Thomas Jew
IPC分类号： G11C7/10
CPC分类号： G11C16/3468 , G11C16/30
摘要： A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.

6. 发明授权

US06745357B2 Dynamic logic scan gate method and apparatus 有权
标题翻译：动态逻辑扫描门法和装置
公开(公告)号：US06745357B2
公开(公告)日：2004-06-01
申请号：US09901411
申请日：2001-07-09
申请人： David W. Chrudimsky , Stephen C. Horne , James S. Blomgren , Michael R. Seningen
发明人： David W. Chrudimsky , Stephen C. Horne , James S. Blomgren , Michael R. Seningen
IPC分类号： G01R3128
CPC分类号： H03K19/096
摘要： A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.
摘要翻译：动态逻辑或N-NARY逻辑的网络990的随机存取扫描的方法和装置，其包括顺序时钟的预充电逻辑门和由从时钟发生电路产生的多个重叠时钟信号驱动的一个或多个扫描门（900） 904），其耦合到时钟脊（902）。每个时钟预充电逻辑门和每个扫描门包括具有一个或多个评估节点的逻辑树（502），预充电电路（32），评估电路（36）和一个或多个输出缓冲器（34）。每个扫描门还包括扫描电路（806），其接收扫描控制信号（406,408,410,824和826）并且以类似RAM的架构耦合到一个或多个扫描寄存器（416）。扫描控制信号操作以捕获扫描门的输出缓冲器的状态，并且迫使扫描门的输出缓冲器达到预选的电平。

7. 发明授权

US08625365B2 Memory device and method using encode values for access error condition detection 有权
标题翻译：存储器件和使用编码值进行访问错误状态检测的方法
公开(公告)号：US08625365B2
公开(公告)日：2014-01-07
申请号：US13212478
申请日：2011-08-18
申请人： Padmaraj Sanjeevarao , David W. Chrudimsky
发明人： Padmaraj Sanjeevarao , David W. Chrudimsky
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/1006
摘要： A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.
摘要翻译：存储器模块解码地址以确定一个或多个字线选择模式或其他空间选择模式。编码器基于与预期编码值进行比较的字线选择模式来确定编码值。编码值的位数少于用于确定字线选择模式的地址位数的两倍。

8. 发明申请

US20090316509A1 MEMORY WITH HIGH SPEED SENSING 有权
标题翻译：高速感应记忆
公开(公告)号：US20090316509A1
公开(公告)日：2009-12-24
申请号：US12144332
申请日：2008-06-23
申请人： Padmaraj Sanjeevarao , Tahmina Akhter , David W. Chrudimsky
发明人： Padmaraj Sanjeevarao , Tahmina Akhter , David W. Chrudimsky
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C7/065 , G11C7/12
摘要： A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.
摘要翻译：包括数据线，读出放大器和存储器单元阵列的存储器。存储器包括用于将数据线耦合到用于读取的阵列的存储器单元的晶体管。晶体管被偏置在高于在预充电期间数据线偏置的电压的电压。晶体管是调节电路的一部分。调节电路包括具有比读出放大器的晶体管更高的介电击穿电压的晶体管。

9. 发明授权

US5991201A Non-volatile memory with over-program protection and method therefor 失效
标题翻译：具有过程编程保护的非易失性存储器及其方法
公开(公告)号：US5991201A
公开(公告)日：1999-11-23
申请号：US067026
申请日：1998-04-27
申请人： Clinton C. K. Kuo , Thomas Jew , David W. Chrudimsky
发明人： Clinton C. K. Kuo , Thomas Jew , David W. Chrudimsky
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3486 , G11C16/3459 , G11C16/3468
摘要： A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.
摘要翻译：浮栅非易失性存储器（30）使用相对低的阈值电压来定义编程状态。存储器（30）通过提供在单元被编程时增加长度和幅度的编程脉冲来补偿快速编程单元。在每个编程脉冲之间，存储器（30）确定所选择的单元是否已被适当编程。当存储器（30）已被适当地编程时，存储器（30）停止向每个单元施加一系列脉冲。因此，存储器（30）避免了过程编程状态，而不是补偿它。

10. 发明授权

US08913436B2 Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage 有权
标题翻译：带有字线驱动器/解码器的非易失性存储器（NVM）使用电荷泵电压
公开(公告)号：US08913436B2
公开(公告)日：2014-12-16
申请号：US13826958
申请日：2013-03-14
申请人： Padmaraj Sanjeevarao , David W. Chrudimsky
发明人： Padmaraj Sanjeevarao , David W. Chrudimsky
IPC分类号： G11C16/06 , G11C8/00 , G11C5/14 , G11C8/08
CPC分类号： G11C8/08 , G11C16/08
摘要： A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.
摘要翻译：一种字线驱动器，其包括用于偏置位于高电源电压端子和低电源电压端子之间的晶体管堆叠的节点的上拉晶体管。节点偏置在高电源电压和低电源电压之间的电压。晶体管堆叠包括一堆解码晶体管和共源共栅晶体管。共源共栅晶体管位于节点和耦合到反相电路的堆叠的第二节点之间。

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