专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06185718B2 Memory card design with parity and ECC for non-parity and non-ECC systems 失效
标题翻译：具有奇偶校验的存储卡设计和非奇偶校验和非ECC系统的ECC
公开(公告)号：US06185718B2
公开(公告)日：2001-02-06
申请号：US09032195
申请日：1998-02-27
申请人： Timothy J. Dell , Kamal E. Dimitri , Kent A. Dramstad , Marc R. Faucher , Bruce G. Hazelzet , Bruce W. Singer
发明人： Timothy J. Dell , Kamal E. Dimitri , Kent A. Dramstad , Marc R. Faucher , Bruce G. Hazelzet , Bruce W. Singer
IPC分类号： G06F1100
CPC分类号： G06F11/1032 , G06F11/326 , G11C29/42
摘要： A memory card design which adds parity for non-parity computer systems to supply error detection capabilities is provided. The apparatus includes a memory card, parity DRAM locatable on the memory card, logic for generating and checking parity bits and logic for the control of the generating, checking and storing parity bits. Also, in another embodiment, the apparatus adds error correction code to the memory card to provide error detection and correction code to systems lacking such capabilities.
摘要翻译：提供了一种为非奇偶校验计算机系统添加奇偶校验以提供错误检测能力的存储卡设计。该装置包括存储卡，位于存储卡上的奇偶校验DRAM，用于产生和检查奇偶校验位的逻辑以及用于控制生成，检查和存储奇偶校验位的逻辑。此外，在另一个实施例中，该装置向存储卡添加纠错码，以向缺少这种能力的系统提供错误检测和校正码。

2. 发明授权

US5870404A Self-timed circuit having critical path timing detection 失效
标题翻译：具有关键路径定时检测的自定时电路
公开(公告)号：US5870404A
公开(公告)日：1999-02-09
申请号：US694120
申请日：1996-08-08
申请人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
发明人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
IPC分类号： G06F1/08 , G06K5/04 , G11B5/00
CPC分类号： G06F1/08
摘要： A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.
摘要翻译：公开了一种用于使用时钟逻辑系统的自定时电路，其包括用于检测关键路径的定时裕度的定时检测装置，该关键路径是限制系统速度的路径。该电路还包括用于增加系统时钟的速度的增加逻辑，如果定时裕度允许的话，并且如果定时裕度表示这样的需要，则降低用于降低系统时钟速度的逻辑。增加和减少逻辑包括阈值发生器和复位逻辑以及时钟控制逻辑。

3. 发明授权

US5634116A Non-integer multiple clock translator 失效
标题翻译：非整数多时钟转换器
公开(公告)号：US5634116A
公开(公告)日：1997-05-27
申请号：US413641
申请日：1995-03-30
申请人： Bruce W. Singer
发明人： Bruce W. Singer
IPC分类号： G11B20/14 , G06F1/12 , H04L7/00 , H04L25/40
CPC分类号： G06F1/12
摘要： A multiple clock translator for a microprocessor is provided for synchronizing data from an external clock speed to an internal clock speed that is a non-integer multiple of the external clock speed. The translator comprises a latch circuit and a synchronization signal generator. The latch circuit receives data at the external clock speed and outputs data at the internal clock speed. The latch circuit includes an input latch and a sync latch, and receives an external clock having an enabling phase and an internal clock having an enabling phase. The input latch is docked by the enabling phase of the external clock, and the sync latch is docked by the enabling phase of the internal clock and enabled by a sync pulse. The synchronization signal generator generates a series of sync pulses that are output to the latch circuit in a selected pattern, wherein the pattern is a function of the non-integer multiple.
摘要翻译：提供了一种用于微处理器的多时钟转换器，用于将数据从外部时钟速度同步到外部时钟速度的非整数倍的内部时钟速度。翻译器包括锁存电路和同步信号发生器。锁存电路以外部时钟速度接收数据，并以内部时钟速度输出数据。锁存电路包括输入锁存器和同步锁存器，并且接收具有使能相位的外部时钟和具有使能相位的内部时钟。输入锁存器通过外部时钟的使能阶段对接，并且同步锁存器被内部时钟的使能阶段锁定，并由同步脉冲使能。同步信号发生器产生一系列以所选模式输出到锁存电路的同步脉冲，其中该模式是非整数倍的函数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式