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1. 发明申请

US20060021514A1 Drawer and latching mechanism for positioning and securing a pod below the brew head of a beverage brewer 有权
公开(公告)号：US20060021514A1
公开(公告)日：2006-02-02
申请号：US11166589
申请日：2005-06-24
申请人： Timothy Gantt , William Dahmen , William Reuss , Kenton Graviss , David Waynescott , Robert Mallory , Kwong Wong , David Vergara
发明人： Timothy Gantt , William Dahmen , William Reuss , Kenton Graviss , David Waynescott , Robert Mallory , Kwong Wong , David Vergara
IPC分类号： A47J31/00
CPC分类号： A47J31/368 , A47J31/0668 , A47J31/4471
摘要： A drawer and latching mechanism for a beverage brewer, and preferably, a brewer that utilizes a pod of coffee grounds or another beverage component, has a housing of the brewer including a pivotable cover and a drawer for retaining a pod of a beverage component below the brew head. In an open position, the pivotable cover and brew head are pivoted away from the drawer to allow access to the pod, while in a closed position, the pivotable cover and brew head are pivoted toward and locked relative to the drawer to secure the pod below the brew head for brewing.

2. 发明申请

US20070128867A1 METHOD FOR ENHANCED UNI-DIRECTIONAL DIFFUSION OF METAL AND SUBSEQUENT SILICIDE FORMATION 审中-公开
标题翻译：金属和后续硅化物形成的增强的单向扩散方法
公开(公告)号：US20070128867A1
公开(公告)日：2007-06-07
申请号：US11672363
申请日：2007-02-07
申请人： Anthony Domenicucci , Bradley Jones , Christian Lavoie , Robert Purtell , Yun Wang , Kwong Wong
发明人： Anthony Domenicucci , Bradley Jones , Christian Lavoie , Robert Purtell , Yun Wang , Kwong Wong
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/28518 , H01L29/665
摘要： The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.
摘要翻译：本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。第一热循环导致形成含非晶态金属的硅化物。第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。提供了一种金属硅化物，其厚度是自限制的。

3. 发明申请

US20070087541A1 METHOD AND APPARATUS FOR DEPOSITION & FORMATION OF METAL SILICIDES 审中-公开
标题翻译：用于沉积和形成金属硅的方法和装置
公开(公告)号：US20070087541A1
公开(公告)日：2007-04-19
申请号：US11557259
申请日：2006-11-07
申请人： Kenneth Giewont , Bradley Jones , Christian Lavoie , Robert Purtell , Yun-Yu Wang , Kwong Wong
发明人： Kenneth Giewont , Bradley Jones , Christian Lavoie , Robert Purtell , Yun-Yu Wang , Kwong Wong
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： C23C14/5806 , C23C14/16
摘要： Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.
摘要翻译：公开了一种在硅材料上形成硅化物的方法和结构。本发明将硅材料置于真空环境中，在硅材料上形成金属，然后在不破坏真空环境的情况下加热硅表面和金属。当金属沉积时，形成金属和加热硅的工艺可以同时进行而不破坏真空环境以形成硅化物。在上述处理之后，本发明可以从真空环境中去除硅表面，并对硅表面进行附加加热。第一加热工艺形成一硅化物，另外的加热形成二硅化物。

4. 发明申请

US20060024733A1 Storing data encoded DNA in living organisms 审中-公开
公开(公告)号：US20060024733A1
公开(公告)日：2006-02-02
申请号：US11233153
申请日：2005-09-21
申请人： Pak Wong , Kwong Wong , Harlan Foote
发明人： Pak Wong , Kwong Wong , Harlan Foote
IPC分类号： C12Q1/68 , C12N1/21 , B41K3/38
CPC分类号： G11C13/0019 , B82Y10/00 , G06N3/123 , G11C13/0014
摘要： Current technologies allow the generation of artificial DNA molecules and/or the ability to alter the DNA sequences of existing DNA molecules. With a careful coding scheme and arrangement, it is possible to encode important information as an artificial DNA strand and store it in a living host safely and permanently. This inventive technology can be used to identify origins and protect R&D investments. It can also be used in environmental research to track generations of organisms and observe the ecological impact of pollutants. Today, there are microorganisms that can survive under extreme conditions. As well, it is advantageous to consider multicellular organisms as hosts for stored information. These living organisms can provide as memory housing and protection for stored data or information. The present invention provides well for data storage in a living organism wherein at least one DNA sequence is encoded to represent data and incorporated into a living organism.

5. 发明申请

US20080036007A1 METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 有权
标题翻译：用于改进PFET器件性能的用于形成具有高压应力的氮化物膜的方法
公开(公告)号：US20080036007A1
公开(公告)日：2008-02-14
申请号：US11875217
申请日：2007-10-19
申请人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
发明人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译：提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。这种压应力允许改进PFET中的器件性能。使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。氮化物层的厚度在约300-2000埃的范围内。

6. 发明申请

US20070007548A1 METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 失效
标题翻译：用于改进PFET器件性能的用于形成具有高压应力的氮化物膜的方法
公开(公告)号：US20070007548A1
公开(公告)日：2007-01-11
申请号：US11160705
申请日：2005-07-06
申请人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
发明人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
IPC分类号： H01L21/8234 , H01L27/10 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译：提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。这种压应力允许改进PFET中的器件性能。使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。氮化物层的厚度在约300-2000埃的范围内。

7. 发明申请

US20060109117A1 Apparatus and Method of Intelligent Multistage System Deactivation 审中-公开
标题翻译：智能多级系统停用的装置与方法
公开(公告)号：US20060109117A1
公开(公告)日：2006-05-25
申请号：US10904664
申请日：2004-11-22
申请人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
发明人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
IPC分类号： G08B13/14
CPC分类号： G06F21/554 , G06F21/81 , G06F21/86
摘要： A deactivation management unit for facilitating an intelligent multistage system deactivation process where the deactivation management unit is flexible, facilitates recovery, and renders reverse engineering nearly impossible after the system has been permanently deactivated.
摘要翻译：一种停用管理单元，用于促进智能多级系统停用过程，其中停用管理单元是灵活的，便于恢复，并且在系统被永久停用之后几乎不可能实现逆向工程。

8. 发明申请

US20060024811A1 Storing data encoded DNA in living organisms 审中-公开
公开(公告)号：US20060024811A1
公开(公告)日：2006-02-02
申请号：US11233178
申请日：2005-09-21
申请人： Pak Wong , Kwong Wong , Harlan Foote
发明人： Pak Wong , Kwong Wong , Harlan Foote
IPC分类号： C12Q1/68 , C12N1/20 , C12N15/74
CPC分类号： G11C13/0019 , B82Y10/00 , G06N3/123 , G11C13/0014
摘要： Current technologies allow the generation of artificial DNA molecules and/or the ability to alter the DNA sequences of existing DNA molecules. With a careful coding scheme and arrangement, it is possible to encode important information as an artificial DNA strand and store it in a living host safely and permanently. This inventive technology can be used to identify origins and protect R&D investments. It can also be used in environmental research to track generations of organisms and observe the ecological impact of pollutants. Today, there are microorganisms that can survive under extreme conditions. As well, it is advantageous to consider multicellular organisms as hosts for stored information. These living organisms can provide as memory housing and protection for stored data or information. The present invention provides well for data storage in a living organism wherein at least one DNA sequence is encoded to represent data and incorporated into a living organism.

9. 发明申请

US20080045039A1 METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 失效
公开(公告)号：US20080045039A1
公开(公告)日：2008-02-21
申请号：US11873721
申请日：2007-10-17
申请人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
发明人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

10. 发明申请

US20050221612A1 A LOW THERMAL BUDGET (MOL) LINER, A SEMICONDUCTOR DEVICE COMPRISING SAID LINER AND METHOD OF FORMING SAID SEMICONDUCTOR DEVICE 审中-公开
标题翻译：低热预算（MOL）衬垫，包含上述衬垫的半导体器件和形成半导体器件的方法
公开(公告)号：US20050221612A1
公开(公告)日：2005-10-06
申请号：US10708978
申请日：2004-04-05
申请人： Laura Brown , Fen Jamin , Kin-Sang Lam , Ying Li , Yun Wang , Horatio Wildman , Kwong Wong
发明人： Laura Brown , Fen Jamin , Kin-Sang Lam , Ying Li , Yun Wang , Horatio Wildman , Kwong Wong
IPC分类号： H01L21/336 , H01L21/425 , H01L21/768 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76856 , H01L21/823814 , H01L21/823835 , H01L21/823871 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： The present invention is directed to a low thermal budget MOL liner to be used in the fabrication of a semiconductor device. The low thermal budget MOL liner of the present invention, which is formed by treating a titanium-deposited layer with an in-situ plasma nitridization step, results in a significantly improved high performance device as the need for the higher thermal annealing process presently used in the making of such devices can be avoided. The present invention is further directed to a method of making the resulting semiconductor device, as well as the semi-conductor device itself.
摘要翻译：本发明涉及一种用于制造半导体器件的低热量预算MOL衬垫。通过用原位等离子体氮化步骤处理钛沉积层形成的本发明的低热量预算MOL衬垫导致了显着改进的高性能器件，因为目前使用的较高热退火工艺可以避免这种装置的制造。本发明还涉及制造所得半导体器件以及半导体器件本身的方法。

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