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1. 发明申请

US20090228751A1 METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE 审中-公开
标题翻译：用于在半导体芯片上执行逻辑内置自测试循环的方法和与测试引擎相关的半导体芯片
公开(公告)号：US20090228751A1
公开(公告)日：2009-09-10
申请号：US12125476
申请日：2008-05-22
申请人： Tilman Gloekler , Christoph Jaeschke , Thuyen Le , Martin Padeffke
发明人： Tilman Gloekler , Christoph Jaeschke , Thuyen Le , Martin Padeffke
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536 , G01R31/318547
摘要： A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.
摘要翻译：一种用于在半导体芯片上执行逻辑内置自检（LBIST）周期的方法，结构和设计系统，其具有多个逻辑电路和多个存储元件，所述多个逻辑电路和多个存储元件串联连接到多个LBIST树桩（图案段）之间，伪随机模式生成器（30）和多输入签名寄存器。半导体芯片被细分为分区，使得LBIST周期可以针对一个或多个分区单独运行或并行运行。 LBIST循环也可以分开运行或在分区之间并行连接。要测试的分区由至少一个对应的时钟信号控制，并且待测试的互连由至少一个相应的时钟信号控制。

2. 发明授权

US07877655B2 Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit 失效
标题翻译：在集成电路上使用LBIST引擎执行测试用例的方法，用于指定集成电路的集成电路和方法
公开(公告)号：US07877655B2
公开(公告)日：2011-01-25
申请号：US11855505
申请日：2007-09-14
申请人： Thuyen Le , Thomas Pflueger , Martin Padeffke , Stefan Bonsels
发明人： Thuyen Le , Thomas Pflueger , Martin Padeffke , Stefan Bonsels
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/318502
摘要： A method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.
摘要翻译：一种在具有根据预定方案互连的多个存储元件和逻辑电路的集成电路上的至少一个LBIST引擎执行测试用例的方法。 LBIST引擎部分由存储元件和/或逻辑电路构成。至少一个扫描链形成为一系列所选择的存储元件，并且其它存储元件用于LBIST引擎或在测试模式中用于所述LBIST引擎的一部分。扫描链由测试模式驱动，LBIST测试用例正在测试对应于所述扫描链的存储元件的逻辑电路的那些部分。

3. 发明授权

US07861129B2 Integrated circuit for writing and reading registers distributed across a semiconductor chip 失效
标题翻译：用于写入和读取分布在半导体芯片上的寄存器的集成电路
公开(公告)号：US07861129B2
公开(公告)日：2010-12-28
申请号：US12109529
申请日：2008-04-25
申请人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
发明人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318555
摘要： An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.
摘要翻译：一种半导体芯片上的集成电路，具有分布在半导体芯片上的多个寄存器。寄存器是可写和可读的。集成电路包括中央控制块。集成电路包括多个电路单元。电路单元包括具有本地时钟控制器和一个或多个寄存器的功能部分。电路单元包括卫星部分。中央控制块和卫星部分串联在一起并形成扫描链，其中扫描链形成为环。

4. 发明申请

US20080270860A1 Integrated Circuit for Writing and Reading Registers Distributed Across a Semiconductor Chip 失效
标题翻译：用于写入和读取寄存器的集成电路分布在半导体芯片中
公开(公告)号：US20080270860A1
公开(公告)日：2008-10-30
申请号：US12109529
申请日：2008-04-25
申请人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
发明人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
IPC分类号： G01R31/28 , G06F11/26
CPC分类号： G01R31/318558 , G01R31/318555
摘要： An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.
摘要翻译：一种半导体芯片上的集成电路，具有分布在半导体芯片上的多个寄存器。寄存器是可写和可读的。集成电路包括中央控制块。集成电路包括多个电路单元。电路单元包括具有本地时钟控制器和一个或多个寄存器的功能部分。电路单元包括卫星部分。中央控制块和卫星部分串联在一起并形成扫描链，其中扫描链形成为环。

5. 发明申请

US20080072111A1 Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit 失效
标题翻译：在集成电路上使用LBIST引擎执行测试用例的方法，用于指定集成电路的集成电路和方法
公开(公告)号：US20080072111A1
公开(公告)日：2008-03-20
申请号：US11855505
申请日：2007-09-14
申请人： Thuyen Le , Thomas Pflueger , Martin Padeffke , Stefan Bonsels
发明人： Thuyen Le , Thomas Pflueger , Martin Padeffke , Stefan Bonsels
IPC分类号： G01R31/3187
CPC分类号： G01R31/3187 , G01R31/318502
摘要： The present invention relates to a method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is at least partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.
摘要翻译：本发明涉及一种在具有根据预定方案互连的多个存储元件和逻辑电路的集成电路上的至少一个LBIST引擎执行测试用例的方法。 LBIST引擎至少部分地由存储元件和/或逻辑电路构成。至少一个扫描链形成为一系列所选择的存储元件，并且其它存储元件用于LBIST引擎或在测试模式中用于所述LBIST引擎的一部分。扫描链由测试模式驱动，LBIST测试用例正在测试对应于所述扫描链的存储元件的逻辑电路的那些部分。

6. 发明授权

US07557614B1 Topology for a n-way XOR/XNOR circuit 失效
标题翻译： n路XOR / XNOR电路拓扑
公开(公告)号：US07557614B1
公开(公告)日：2009-07-07
申请号：US12173569
申请日：2008-07-15
申请人： Stefan Bonsels , Martin Padeffke , Tobias Werner , Alexander Woerner
发明人： Stefan Bonsels , Martin Padeffke , Tobias Werner , Alexander Woerner
IPC分类号： H03K19/21
CPC分类号： H03K19/215
摘要： A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.
摘要翻译：一种用于配置n路XOR / XNOR电路的方法包括提供多个顶层堆叠PFET，每个PFET包括电连接在高逻辑电平和输出逻辑连接之间的至少三个PFET，提供多个NFET堆叠，每个NFET包括电连接在低逻辑电平和输出逻辑连接之间的至少三个NFET，将每个顶部堆叠中的最外侧PFET的源极或漏极连接到每个底部堆叠中的相应NFET的源极或漏极，以产生反相逻辑信号将至少三个输入逻辑状态输入到PFET的堆叠中，以选择性地将输出逻辑连接连接或断开到高逻辑电平，将至少三个输入逻辑状态输入到NFET堆，以有选择地将输出逻辑连接低逻辑电平，并从输出逻辑连接输出逻辑信号。

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