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1. 发明授权

US07141845B2 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US07141845B2
公开(公告)日：2006-11-28
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

2. 发明申请

US20050088895A1 DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
标题翻译：具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法
公开(公告)号：US20050088895A1
公开(公告)日：2005-04-28
申请号：US10897687
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
IPC分类号： G11C11/34
CPC分类号： H01L27/10841 , H01L27/10867
摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.
摘要翻译：在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏极电容的减小以及栅电极和漏极电极之间的漏电流较低的源极/漏极区域。施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构单元晶体管。

3. 发明授权

US07109544B2 Architecture for vertical transistor cells and transistor-controlled memory cells 有权
标题翻译：垂直晶体管单元和晶体管控制存储单元的架构
公开(公告)号：US07109544B2
公开(公告)日：2006-09-19
申请号：US10777128
申请日：2004-02-13
申请人： Till Schloesser , Dirk Manger , Bernd Goebel
发明人： Till Schloesser , Dirk Manger , Bernd Goebel
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.
摘要翻译：在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。晶体管单元的较低源极/漏极区域连接到公共连接板。晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。字线形成栅电极。在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。

4. 发明申请

US20050083724A1 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US20050083724A1
公开(公告)日：2005-04-21
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： G11C11/34 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

5. 发明申请

US20050001257A1 Method of fabricating and architecture for vertical transistor cells and transistor-controlled memory cells 有权
标题翻译：垂直晶体管单元和晶体管控制存储单元的制造和架构方法
公开(公告)号：US20050001257A1
公开(公告)日：2005-01-06
申请号：US10777128
申请日：2004-02-13
申请人： Till Schloesser , Dirk Manger , Bernd Goebel
发明人： Till Schloesser , Dirk Manger , Bernd Goebel
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.
摘要翻译：在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。晶体管单元的较低源极/漏极区域连接到公共连接板。晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。字线形成栅电极。在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。

6. 发明申请

US20080054324A1 INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE 有权
标题翻译：集成电路，包括门电极
公开(公告)号：US20080054324A1
公开(公告)日：2008-03-06
申请号：US11926653
申请日：2007-10-29
申请人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
发明人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
IPC分类号： H01L29/94
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅电极在至少两个相对的两侧包围沟道层。

7. 发明申请

US20060079049A1 Method for fabricating a capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US20060079049A1
公开(公告)日：2006-04-13
申请号：US11223800
申请日：2005-09-09
申请人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
发明人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).
摘要翻译：在制造包括电极结构（80）的电容器的方法中，辅助层（40）形成在衬底（10）上。确定电极结构（80）的形状的凹部（60）被蚀刻到辅助层（40）中，电容器的电极结构形成在凹部中。作为示例，辅助层可以是半导体层（40）。

8. 发明授权

US07863149B2 Method for fabricating a capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US07863149B2
公开(公告)日：2011-01-04
申请号：US11223800
申请日：2005-09-09
申请人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
发明人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).
摘要翻译：在制造包括电极结构（80）的电容器的方法中，辅助层（40）形成在衬底（10）上。确定电极结构（80）的形状的凹部（60）被蚀刻到辅助层（40）中，电容器的电极结构形成在凹部中。作为示例，辅助层可以是半导体层（40）。

9. 发明申请

US20070114616A1 Field effect transistor and method of manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070114616A1
公开(公告)日：2007-05-24
申请号：US11287151
申请日：2005-11-23
申请人： Dirk Manger , Till Schloesser
发明人： Dirk Manger , Till Schloesser
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/2815 , H01L27/10873 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said gate electrode. A gate oxide layer is formed upon the semiconductor substrate. The gate electrode contacts a surface of the gate oxide layer and further comprises at least a first and a second conductive layer, wherein the first and second conductive layers are made of materials having different work functions with respect to each other. The first conductive layer contacts the gate oxide layer within a first portion of the surface, and the second conductive layer contacts the gate oxide layer within a second portion of the surface. The first conductive layer is further conductively connected to the second conductive layer.
摘要翻译：布置在半导体器件中的场效应晶体管包括第一和第二掺杂源极/漏极区域，两个区域布置在栅电极的任一侧上的半导体衬底内，以及形成在衬底内的沟道区域在所述栅电极下方的掺杂源/漏区两者。在半导体衬底上形成栅氧化层。栅极电极接触栅极氧化物层的表面，并且还包括至少第一和第二导电层，其中第一和第二导电层由相对于彼此具有不同功函数的材料制成。第一导电层在表面的第一部分内接触栅极氧化物层，并且第二导电层在表面的第二部分内接触栅极氧化物层。第一导电层进一步导电连接到第二导电层。

10. 发明授权

US06932916B2 Semiconductor substrate with trenches of varying depth 失效
标题翻译：具有不同深度的沟槽的半导体衬底
公开(公告)号：US06932916B2
公开(公告)日：2005-08-23
申请号：US10425179
申请日：2003-04-29
申请人： Dirk Manger , Hans-Peter Moll , Till Schloesser
发明人： Dirk Manger , Hans-Peter Moll , Till Schloesser
IPC分类号： H01L21/308 , H01L21/334 , H01L21/762 , H01L21/8242 , B44C1/22 , H01L21/302
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76229 , H01L27/1087 , H01L29/66181
摘要： A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.
摘要翻译：在半导体衬底上蚀刻具有不同深度的沟槽的方法包括：提供具有第一和第二开口的掩模。第一和第二开口位于相应的第一和第二沟槽将被蚀刻的位置。在对应于第二开口的位置处，在衬底上方设置由缓蚀刻材料制成的缓蚀刻区域。当暴露于所选择的蚀刻剂时，以暴露于所选择的蚀刻剂的半导体衬底被蚀刻的速率小的速率蚀刻慢刻蚀材料。

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