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1. 发明授权

US06507091B1 Transistor with indium-implanted SiGe alloy and processes for fabricating the same 失效
标题翻译：具有铟注入SiGe合金的晶体管及其制造方法
公开(公告)号：US06507091B1
公开(公告)日：2003-01-14
申请号：US09515787
申请日：2000-02-29
申请人： Thomas Skotnicki , Jérôme Alieu
发明人： Thomas Skotnicki , Jérôme Alieu
IPC分类号： H01L310328
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/76224 , H01L29/1054
摘要： An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided. Germanium is implanted into at least one region of a silicon substrate where a channel region of a transistor is to be formed, in order to form a buried layer of an Si1−xGex alloy in which 10−5≦x≦4×10−1. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer.
摘要翻译：提供了一种注入铟的晶体管。晶体管具有硅沟道区，其包括其中注入铟的Si1-xGex合金的掩埋层，其中10-5≤x≤4×10-1。还提供了用于制造铟注入晶体管的第一种方法。在硅衬底的表面的至少一个区域上制造多层复合膜，其中要形成晶体管的沟道区。该多层复合膜包括至少一个Si1-xGex合金层，其中10-5 <= x <= 4×10-1，以及外部硅层。将铟注入到Si1-xGex合金层中，并完成晶体管的制造，以便制造具有包含掩埋的Si1-xGex合金层的沟道区的晶体管。另外，提供了用于制造铟注入晶体管的第二种方法。将锗注入到要形成晶体管的沟道区的硅衬底的至少一个区域中，以形成Si1-xGex合金的掩埋层，其中10-5≤x≤4×10-1 。将铟注入到Si1-xGex合金层中，并完成晶体管的制造，以便制造具有包含掩埋的Si1-xGex合金层的沟道区的晶体管。

2. 发明授权

US06528399B1 MOSFET transistor with short channel effect compensated by the gate material 有权
标题翻译：具有沟道效应的MOSFET晶体管由栅极材料补偿
公开(公告)号：US06528399B1
公开(公告)日：2003-03-04
申请号：US09606600
申请日：2000-06-29
申请人： Jérôme Alieu , Caroline Hernandez , Michel Haond
发明人： Jérôme Alieu , Caroline Hernandez , Michel Haond
IPC分类号： H01L2122
CPC分类号： H01L29/4983 , H01L21/28105
摘要： A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in that the gate comprises side regions presenting an increasing germanium percentage towards the sides of the gate facing the drain and source regions. Advantage: compensation of the short channel effect by locally decreasing the work function of the gate material near the drain and source regions.
摘要翻译：一种MOSFET晶体管，包括由硅 - 锗合金构成的栅极，其通过薄绝缘层在单晶硅衬底上形成，并且漏极和源极区域注入到栅极的每一侧上的衬底中，其特征在于栅极包括侧面区域朝着面向漏极和源极区域的栅极的侧面呈现增加的锗百分比。优点：通过局部降低漏极和源极区附近栅极材料的功函来补偿短沟道效应。

3. 发明授权

US08044443B2 Photosensitive integrated circuit equipped with a reflective layer and corresponding method of production 有权
标题翻译：光敏集成电路配有反射层和相应的生产方法
公开(公告)号：US08044443B2
公开(公告)日：2011-10-25
申请号：US11603961
申请日：2006-11-21
申请人： Jérôme Alieu , Simon Guillaumet , Christophe Legendre , Hugues Leininger , Jean-Pierre Oddou , Marc Vincent
发明人： Jérôme Alieu , Simon Guillaumet , Christophe Legendre , Hugues Leininger , Jean-Pierre Oddou , Marc Vincent
IPC分类号： H01L29/04
CPC分类号： H01L27/14643 , H01L27/1462 , H01L27/14632
摘要： A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
摘要翻译：一种制造感光集成电路的方法，包括制造电路控制晶体管，在控制晶体管之上以及在至少一个上电极和至少一个下电极，至少一个光电二极管之间，通过非晶硅层产生入射电磁波的光子辐射被吸收，在下电极和控制晶体管之间产生至少一个钝化层，并且在控制晶体管和集成电路的外表面之间产生能够反射未被非晶硅层吸收的光子的反射层。

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