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1. 发明申请

US20050083921A1 Router switch fabric protection using forward error correction 有权
标题翻译：路由器交换矩阵保护采用前向纠错
公开(公告)号：US20050083921A1
公开(公告)日：2005-04-21
申请号：US10981841
申请日：2004-11-05
申请人： Thomas McDermott , Harry Blackmon , Tony Brewer , Harold Dozier , Jim Kleiner , Gregory Palmer , Keith Shaw , David Traylor , Dean Walker
发明人： Thomas McDermott , Harry Blackmon , Tony Brewer , Harold Dozier , Jim Kleiner , Gregory Palmer , Keith Shaw , David Traylor , Dean Walker
IPC分类号： H04L12/56 , H04Q11/00 , H04Q11/04 , H04L12/50
CPC分类号： H04Q11/0005 , H04J2203/0057 , H04L49/1523 , H04L49/208 , H04L49/254 , H04L49/357 , H04L2012/5627 , H04Q11/0066 , H04Q2011/0043
摘要： Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric. Under error-free normal conditions, however, the PFMs select a chunk arbitrarily from a default switch fabric. In this way, each chunk in real time is selected from a non-defective source and is thus guaranteed to be error free. Accordingly, if a switch fabric fails, no information chunks are lost anywhere in the system.
摘要翻译：代替替代地仅使用冗余对的一个结构或另一个结构，两个结构同时发送重复信息，使得每个分组转发模块（PFM）同时接收两个结构的输出。实时地，内部光学模块（IOM）分析从工作的零交换结构出来的每个信息块; 同时检查工作的一个重复交换矩阵的并行输出; 并且以逐块为基础比较来自两个交换结构的每个块的有效性。 IOM通过检查封装到每个块中的前向纠错（FEC）校验符号来实现。 FEC检查符号允许校正块内的预定数量的位错误。如果块不能被纠正，则IOM向下游的所有PFM提供指示该块是有缺陷的。在这种情况下，PFM从无缺陷的交换结构中选择一个块。然而，在无错误的正常条件下，PFM从默认的交换结构中任意选择一个块。以这种方式，从无缺陷源选择实时的每个块，并且因此被保证是无错误的。因此，如果交换机结构发生故障，系统中的任何地方都不会丢失任何信息块。

2. 发明申请

US20060062233A1 System and method for router queue and congestion management 有权
标题翻译：路由器队列和拥塞管理的系统和方法
公开(公告)号：US20060062233A1
公开(公告)日：2006-03-23
申请号：US11272998
申请日：2005-11-14
申请人： Tony Brewer , Jim Kleiner , Gregory Palmer , Keith Shaw
发明人： Tony Brewer , Jim Kleiner , Gregory Palmer , Keith Shaw
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/32 , H04L47/10 , H04L47/24 , H04L49/3081 , H04L2012/5648 , H04L2012/5681 , H04Q11/0478
摘要： In a multi-QOS level queuing structure, packet payload pointers are stored in multiple queues and packet payloads in a common memory pool. Algorithms control the drop probability of packets entering the queuing structure. Instantaneous drop probabilities are obtained by comparing measured instantaneous queue size with calculated minimum and maximum queue sizes. Non-utilized common memory space is allocated simultaneously to all queues. Time averaged drop probabilities follow a traditional Weighted Random Early Discard mechanism. Algorithms are adapted to a multi-level QOS structure, floating point format, and hardware implementation. Packet flow from a router egress queuing structure into a single egress port tributary is controlled by an arbitration algorithm using a rate metering mechanism. The queuing structure is replicated for each egress tributary in the router system.
摘要翻译：在多QOS级别排队结构中，分组有效载荷指针被存储在公共存储器池中的多个队列和分组有效载荷中。算法控制进入排队结构的数据包的丢弃概率。通过将测量的瞬时队列大小与计算的最小和最大队列大小进行比较，可以获得瞬时丢弃概率。未使用的公共存储器空间被同时分配给所有队列。时间平均下降概率遵循传统的加权随机早期丢弃机制。算法适用于多级QOS结构，浮点格式和硬件实现。从路由器出口排队结构到单个出口端口支路的分组流由使用速率计量机制的仲裁算法控制。对路由器系统中的每个出口支路进行排队结构的复制。

3. 发明授权

US08205066B2 Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor 有权
标题翻译：用于不同扩展指令集的动态配置协处理器，具有专用于应用程序的个人特征，共享存储器存储从主机处理器不可见地分派的指令
公开(公告)号：US08205066B2
公开(公告)日：2012-06-19
申请号：US12263203
申请日：2008-10-31
申请人： Tony Brewer , Steven J. Wallach
发明人： Tony Brewer , Steven J. Wallach
IPC分类号： G06F15/16
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/3877 , G06F9/3887 , G06F9/3897
摘要： A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.
摘要翻译：提供了一种协处理器，其包括可被动态配置为期望个性的一个或多个应用引擎。例如，应用引擎可以被动态配置为多个不同的向量处理指令集中的任何一个，例如单精度向量处理指令集和双精度向量处理指令集。协处理器还包括在所有不同个性之间共同的公共基础设施，例如指令解码基础设施，存储器管理基础设施，系统接口基础设施和/或标量处理单元（具有基本指令集）。因此，协处理器的个性可以被动态修改（通过重新配置协处理器的一个或多个应用引擎），而协处理器的公共基础设施在各个人物之间保持一致。

4. 发明授权

US08122229B2 Dispatch mechanism for dispatching instructions from a host processor to a co-processor 有权
标题翻译：用于从主处理器向协处理器分派指令的调度机制
公开(公告)号：US08122229B2
公开(公告)日：2012-02-21
申请号：US11854432
申请日：2007-09-12
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F9/00 , G06F7/44
CPC分类号： G06F9/3877 , G06F9/30185 , G06F9/3802 , G06F9/3879 , G06F9/3897 , G06F12/0855 , G06F12/10 , G06F15/7867
摘要： A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.
摘要翻译：提供了一种调度机制，用于将可执行程序的指令从主处理器分派到异构协处理器。根据某些实施例，在主处理器和异构协处理器之间保持高速缓存一致性，并且利用这种高速缓存一致性来调度由协处理器处理的可执行程序的指令。例如，在某些实施例中，利用指定的存储器部分（例如，“UCB”），其中主处理器可以将信息放置在这样的UCB中，并且协处理器可以从UCB检索信息（反之亦然）。因此，UCB可以用于分派可执行程序的指令以供协处理器处理。在某些实施例中，协处理器可以包括使得协处理器的指令集能够动态改变的动态可重配置逻辑，并且调度操作可以识别要加载到协处理器上的多个预定义指令集中的一个。

5. 发明授权

US08561037B2 Compiler for generating an executable comprising instructions for a plurality of different instruction sets 有权
标题翻译：用于生成包括用于多个不同指令集的指令的可执行程序的编译器
公开(公告)号：US08561037B2
公开(公告)日：2013-10-15
申请号：US11847169
申请日：2007-08-29
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.
摘要翻译：提供了一种软件编译器，其可操作用于生成包括多处理器系统中不同处理器可能采用的多个不同指令集的指令的可执行程序。编译器可以生成包括要由第一指令集（例如，多处理器系统中的第一处理器的第一指令集）处理的指令的第一部分和要由第一指令处理的指令的第二部分的可执行程序第二指令集（诸如多处理器系统中的第二处理器的第二指令集）。这样的可执行程序可以被生成用于在包括至少一个主机处理器的多处理器系统上执行，所述至少一个主处理器可以包括诸如公知的x86指令集之类的固定指令集，以及至少一个协处理器，其包括动态地可配置逻辑，使协处理器的指令集能够动态重新配置。

6. 发明授权

US08156307B2 Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set 有权
标题翻译：具有至少一个包括动态可重构指令集的处理器的多处理器系统
公开(公告)号：US08156307B2
公开(公告)日：2012-04-10
申请号：US11841406
申请日：2007-08-20
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F12/00 , G06F15/76
CPC分类号： G06F15/7867 , G06F9/24 , G06F9/3881 , G06F9/3897
摘要： A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co-processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.
摘要翻译：多处理器系统包括至少一个主机处理器，其可以包括固定指令集，诸如公知的x86指令集。该系统还包括至少一个协处理器，其包括使协处理器的指令集能够动态重新配置的动态可重配置逻辑。以这种方式，至少一个主机处理器和至少一个动态可重配置协处理器是具有不同指令集的异构处理器。此外，在异构主机和协处理器之间保持高速缓存一致性。并且，单个可执行文件可以包含由多处理器系统处理的指令，其中指令的一部分由主机处理器处理，并且指令的一部分由协处理器处理。

7. 发明申请

US20090064095A1 COMPILER FOR GENERATING AN EXECUTABLE COMPRISING INSTRUCTIONS FOR A PLURALITY OF DIFFERENT INSTRUCTION SETS 有权
标题翻译：用于生成多个不同指令集的可执行包含指令的编译器
公开(公告)号：US20090064095A1
公开(公告)日：2009-03-05
申请号：US11847169
申请日：2007-08-29
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/447
摘要： A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.
摘要翻译：提供了一种软件编译器，其可操作用于生成包括多处理器系统中不同处理器可能采用的多个不同指令集的指令的可执行程序。编译器可以生成包括要由第一指令集（例如，多处理器系统中的第一处理器的第一指令集）处理的指令的第一部分和要由第一指令处理的指令的第二部分的可执行程序第二指令集（诸如多处理器系统中的第二处理器的第二指令集）。这样的可执行程序可以被生成用于在包括至少一个主机处理器的多处理器系统上执行，所述至少一个主处理器可以包括诸如公知的x86指令集之类的固定指令集，以及至少一个协处理器，其包括动态地可配置逻辑，使协处理器的指令集能够动态重新配置。

8. 发明授权

US08423745B1 Systems and methods for mapping a neighborhood of data to general registers of a processing element 有权
标题翻译：用于将数据邻域映射到处理元件的通用寄存器的系统和方法
公开(公告)号：US08423745B1
公开(公告)日：2013-04-16
申请号：US12619441
申请日：2009-11-16
申请人： Tony Brewer
发明人： Tony Brewer
IPC分类号： G06F12/00
CPC分类号： G06F9/00 , G06F9/3012 , G06F9/30138 , G06F9/3889 , G06T1/60
摘要： The present invention is directed to systems and methods for mapping a neighborhood of data to general registers of a processing element. Embodiments of the present invention provide techniques for mapping a neighborhood of data to general registers that are “neighborhood constrained” because the general register set is of insufficient size in one or more dimensions to fully store a desired neighborhood of data in a manner that maintains the positional arrangement of such data. However, a window access method is employed for mapping the neighborhood of data to the general register set, thereby enabling the neighborhood of data to be stored to the general register set in a manner that maintains the positional arrangement of such data as may be desired for performing nearest-neighbor types of operations by the processing element.
摘要翻译：本发明涉及用于将数据附近映射到处理元件的通用寄存器的系统和方法。本发明的实施例提供了用于将数据的邻域映射到邻域约束的通用寄存器的技术，因为通用寄存器组在一个或多个维度上的尺寸不足以完全存储期望的数据附近以维持位置布置的方式的数据。然而，采用窗口访问方法将数据的邻域映射到通用寄存器集合，从而使数据的邻域可以以保持这种数据的位置布置的方式存储到通用寄存器集合中，由处理元素执行最近邻操作类型。

9. 发明申请

US20100115237A1 CO-PROCESSOR INFRASTRUCTURE SUPPORTING DYNAMICALLY-MODIFIABLE PERSONALITIES 有权
标题翻译：协同处理基础设施支持动态修改的个人
公开(公告)号：US20100115237A1
公开(公告)日：2010-05-06
申请号：US12263203
申请日：2008-10-31
申请人： Tony Brewer , Steven J. Wallach
发明人： Tony Brewer , Steven J. Wallach
IPC分类号： G06F15/76 , G06F12/00 , G06F9/02
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/3877 , G06F9/3887 , G06F9/3897
摘要： A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.
摘要翻译：提供了一种协处理器，其包括可被动态配置为期望个性的一个或多个应用引擎。例如，应用引擎可以被动态配置为多个不同的向量处理指令集中的任何一个，例如单精度向量处理指令集和双精度向量处理指令集。协处理器还包括在所有不同个性之间共同的公共基础设施，例如指令解码基础设施，存储器管理基础设施，系统接口基础设施和/或标量处理单元（具有基本指令集）。因此，协处理器的个性可以被动态修改（通过重新配置协处理器的一个或多个应用引擎），而协处理器的公共基础设施在不同的个性之间保持一致。

10. 发明申请

US20090070553A1 DISPATCH MECHANISM FOR DISPATCHING INSTURCTIONS FROM A HOST PROCESSOR TO A CO-PROCESSOR 有权
标题翻译：用于将主机处理器分配给CO处理器的调度机制
公开(公告)号：US20090070553A1
公开(公告)日：2009-03-12
申请号：US11854432
申请日：2007-09-12
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3877 , G06F9/30185 , G06F9/3802 , G06F9/3879 , G06F9/3897 , G06F12/0855 , G06F12/10 , G06F15/7867
摘要： A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.
摘要翻译：提供了一种调度机制，用于将可执行程序的指令从主处理器分派到异构协处理器。根据某些实施例，在主处理器和异构协处理器之间保持高速缓存一致性，并且利用这种高速缓存一致性来调度由协处理器处理的可执行程序的指令。例如，在某些实施例中，利用指定的存储器部分（例如，“UCB”），其中主处理器可以将信息放置在这样的UCB中，并且协处理器可以从UCB检索信息（反之亦然）。因此，UCB可以用于分派可执行程序的指令以供协处理器处理。在某些实施例中，协处理器可以包括使得协处理器的指令集能够动态改变的动态可重配置逻辑，并且调度操作可以识别要加载到协处理器上的多个预定义指令集中的一个。

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