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1. 发明授权

US4665482A Data multiplex control facility 失效
标题翻译：数据复用控制设备
公开(公告)号：US4665482A
公开(公告)日：1987-05-12
申请号：US503963
申请日：1983-06-13
申请人： Thomas L. Murray, Jr. , James W. Stonier , Gary J. Goss , Thomas O. Holtey
发明人： Thomas L. Murray, Jr. , James W. Stonier , Gary J. Goss , Thomas O. Holtey
IPC分类号： G06F13/28 , G06F15/167 , G06F3/00 , G06F13/00
CPC分类号： G06F15/167 , G06F13/285
摘要： A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller. The CPU then retrieves the address and range information from the mailbox location and initiates a DMC cycle.
摘要翻译：数据处理系统包括中央处理单元（CPU），输入/输出微处理器，主存储器和多个大容量存储控制器。在数据多路复用控制（DMC）周期期间，一块信息在大容量存储控制器和主存储器之间传送。 CPU包括存储下一个数据字节被写入或读取的主存储器的地址的寄存器以及指示待传送的数据字节数的范围。在DMC循环之前，CPU将地址和范围信息存储在I / O RAM中的邮箱位置，I / O微处理器将该信息传输到I / O RAM中的通道表位置。对于DMC操作，I / O微处理器将地址和范围信息传送到邮箱位置，并将大容量存储信息传输到大容量存储控制器。它发出CPU中断信号，向大容量存储控制器发出读或写命令。 CPU然后从邮箱位置检索地址和范围信息，并启动DMC循环。

2. 发明授权

US4665481A Speeding up the response time of the direct multiplex control transfer facility 失效
标题翻译：加快直接多路复用控制传输设施的响应时间
公开(公告)号：US4665481A
公开(公告)日：1987-05-12
申请号：US503962
申请日：1983-06-13
申请人： James W. Stonier , Thomas L. Murray, Jr. , Gary J. Goss , Thomas O. Holtey
发明人： James W. Stonier , Thomas L. Murray, Jr. , Gary J. Goss , Thomas O. Holtey
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00
CPC分类号： G06F13/285
摘要： A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.
摘要翻译：微程序数据处理系统包括中央处理单元（CPU），主存储器和多个大容量存储控制器。在数据多路复用控制（DMC）周期期间，一块信息在主存储器和大容量存储控制器之一之间传送。主存储器在每个字位置存储2个数据字节。输入/输出RAM存储用于识别大容量存储控制器的通道号信号。 I / O微处理器将I / O RAM寻址到系统总线上的通道号信号，耦合到系统总线的大容量存储控制器响应信道号信号以产生读/写信号。系统响应请求信号，读/写信号和指示主存储器中寻址位置的左或右位的信号，以产生多个数据请求信号。响应于数据请求信号寻址只读存储器以读出用于处理数据的多个微程序。

3. 发明授权

US4945473A Communications controller interface 失效
标题翻译：通信控制器接口
公开(公告)号：US4945473A
公开(公告)日：1990-07-31
申请号：US051084
申请日：1987-05-15
申请人： Thomas O. Holtey , Thomas L. Murray, Jr. , Scott W. Smith , Wayne A. Perzan
发明人： Thomas O. Holtey , Thomas L. Murray, Jr. , Scott W. Smith , Wayne A. Perzan
IPC分类号： G06F13/10 , H04L29/06
CPC分类号： G06F13/10 , H04L29/06
摘要： A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit. These control elements are interconnected to the interface control unit and to the interface memory so that the multi-line communications unit is able to access different ones of the control locations for updating the status of the lines and further enabling the microprocessor-controlled interface control unit to transfer data to and from the transmit data and receive data locations of the lines in the predetermined sequence consistent with the status.
摘要翻译：一种通信控制器接口，用于仿真先前系统，采用多个发送和接收数据的线路单元。接口包括微处理器控制的接口控制单元，其具有具有多个可寻址存储位置的接口存储器。通过将接口存储器划分成与通信线路数量相对应的多个位置组，将每组位置细分为另外的位置，包括用于存储接收数据的位置，用于存储发送数据的位置，以及控制位置。存在多个控制元件，用于生成用于由接口控制单元执行的不同任务的信号序列。这些控制元件互连到接口控制单元和接口存储器，使得多线通信单元能够访问不同的控制位置以更新线路的状态，并且进一步启用微处理器控制的接口控制单元将数据传输到发送数据和从发送数据传送数据，并以与状态一致的预定顺序接收线路的数据位置。

4. 发明授权

US4965721A Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication 失效
标题翻译：用于控制包括多个数据通信线路中的测试操作的处理排序的固件状态设备
公开(公告)号：US4965721A
公开(公告)日：1990-10-23
申请号：US32896
申请日：1987-03-31
申请人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
发明人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
IPC分类号： G06F9/46 , G06F13/00 , G06F13/12 , H04Q3/545
CPC分类号： G06F13/124 , H04Q3/54583
摘要： A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications system and computer system. At least one processor having a program counter is employed for control data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor. The processor, in response to the group of instructions, performs a designated operation for the line and in particular in response to the test instruction loads a new value corresponding to the starting instruction of the group of instructions of the next state.

5. 发明授权

US4979104A Dual microprocessor control system 失效
标题翻译：双微处理器控制系统
公开(公告)号：US4979104A
公开(公告)日：1990-12-18
申请号：US32902
申请日：1987-03-31
申请人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
发明人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
IPC分类号： G06F15/16 , G06F13/00 , G06F13/12 , G06F15/167 , H04L29/02
CPC分类号： G06F15/167 , G06F13/124
摘要： A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an incrementing manner while the other accesses in decrementing manner. When one microprocessor gains access to a specific line table excludes the other microprocessor from accessing that line table until the first microprocessor suspends off of that line table.

6. 发明授权

US4667329A Diskette subsystem fault isolation via video subsystem loopback 失效
标题翻译：磁盘子系统故障隔离通过视频子系统回送
公开(公告)号：US4667329A
公开(公告)日：1987-05-19
申请号：US445608
申请日：1982-11-30
申请人： Thomas L. Murray, Jr. , James C. Siwik , Thomas O. Holtey
发明人： Thomas L. Murray, Jr. , James C. Siwik , Thomas O. Holtey
IPC分类号： G06F3/06 , G06F3/14 , G06F11/22 , G06F11/267 , G01R31/28
CPC分类号： G06F11/2221
摘要： A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.
摘要翻译：数据处理系统包括阴极射线管（CRT）显示子系统和软盘子系统。通过以固定频率调制（MFM）模式生成和传送固定格式的数据比特流从CRT显示子系统到软盘子系统来验证两个系统的逻辑，并根据原始信息检查软盘子系统接收到的信息呈现给CRT显示子系统。

7. 发明授权

US4639858A Apparatus and method for testing and verifying the refresh logic of dynamic MOS memories 失效
标题翻译：用于测试和验证动态MOS存储器的刷新逻辑的装置和方法
公开(公告)号：US4639858A
公开(公告)日：1987-01-27
申请号：US510711
申请日：1983-07-05
申请人： Thomas L. Murray, Jr. , Thomas O. Holtey
发明人： Thomas L. Murray, Jr. , Thomas O. Holtey
IPC分类号： G06F12/16 , G11C11/401 , G11C29/00 , G11C29/02 , G06F13/00 , G11C7/00
CPC分类号： G11C29/02
摘要： The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.
摘要翻译：数据处理系统的动态MOS存储器子系统的刷新逻辑通过提供用于对刷新周期进行计数的装置并在预定次数的刷新周期之后产生处于第一状态的计数器输出信号来测试。微处理器周期性地测试计数器输出信号的状态，并保持对计数器输出信号进行测试并发现处于第二状态的次数的计数。当微处理器在第一状态下测试并发现计数器输出信号时，微处理器将其测试次数与计数器输出信号的次数进行比较，并确定该计数是否在正确操作的预定范围内。

8. 发明授权

US4631699A Firmware simulation of diskette data via a video signal 失效
标题翻译：通过视频信号对软盘数据进行固件仿真
公开(公告)号：US4631699A
公开(公告)日：1986-12-23
申请号：US445631
申请日：1982-11-30
申请人： James C. Siwik , Thomas L. Murray, Jr. , Thomas O. Holtey
发明人： James C. Siwik , Thomas L. Murray, Jr. , Thomas O. Holtey
IPC分类号： G06F3/06 , G06F3/14 , G06F11/22 , G06F11/267 , G06F11/00
CPC分类号： G06F11/2221
摘要： A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.The bit rate of the data stream is varied depending on the number of address locations used in the data RAM of the CRT display subsystem to store each data bit.
摘要翻译：数据处理系统包括阴极射线管（CRT）显示子系统和软盘子系统。通过以固定频率调制（MFM）模式生成和传送固定格式的数据比特流从CRT显示子系统到软盘子系统来验证两个系统的逻辑，并根据原始信息检查软盘子系统接收到的信息呈现给CRT显示子系统。数据流的比特率根据用于存储每个数据位的CRT显示子系统的数据RAM中使用的地址位置的数量而变化。

9. 发明授权

US4586129A Apparatus and method for testing and verifying the timing logic of a cathode ray tube display 失效
标题翻译：用于测试和验证阴极射线管显示器的定时逻辑的装置和方法
公开(公告)号：US4586129A
公开(公告)日：1986-04-29
申请号：US510712
申请日：1983-07-05
申请人： Thomas L. Murray, Jr. , Kin C. Yu , Thomas O. Holtey
发明人： Thomas L. Murray, Jr. , Kin C. Yu , Thomas O. Holtey
IPC分类号： H04N7/173 , G01R31/28 , G06F11/00 , G09G3/00 , G09G5/00 , G06F3/153 , H04N5/04
CPC分类号： G09G3/006 , G01R31/2834 , G06F11/0757
摘要： A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.
摘要翻译：数据处理系统包括阴极射线管（CRT）显示器。与CRT测试相关联的设备，并验证垂直和水平同步以及与字符发生器相关联的逻辑。对来自字符发生器的刷新信号，水平同步信号和数据位信号进行计数。验证在预定数量的垂直同步信号中发生的那些信号的计数。

10. 发明授权

US4494186A Automatic data steering and data formatting mechanism 失效
标题翻译：自动数据转向和数据格式化机制
公开(公告)号：US4494186A
公开(公告)日：1985-01-15
申请号：US286444
申请日：1981-07-24
申请人： Gary J. Goss , Richard P. Kelly , Thomas L. Murray, Jr.
发明人： Gary J. Goss , Richard P. Kelly , Thomas L. Murray, Jr.
IPC分类号： G06F5/00 , G06F13/38 , G06F3/00
CPC分类号： G06F13/387 , G06F5/00
摘要： In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.
摘要翻译：在具有多个单元的数据处理系统中，所述多个单元耦合用于通过公共电气总线传递信息，或者用于在异步生成的信息总线传送周期期间经由通信信道将信息传送到其他数据处理系统，存在用于重新格式化数据的设备通过公共电气总线或通过通信信道进行传输。该装置包括一个八路复用器，响应于控制位，用于在从存储器写入或读取操作期间选择八种不同格式之一。此外，在读取操作期间，设备将请求信息的单元的返回地址传送到地址总线，从而可以将从存储器读取的数据传送到请求设备。格式控制位类似地从数据总线重新格式化为地址总线位。

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