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1. 发明授权

US4945473A Communications controller interface 失效
标题翻译：通信控制器接口
公开(公告)号：US4945473A
公开(公告)日：1990-07-31
申请号：US051084
申请日：1987-05-15
申请人： Thomas O. Holtey , Thomas L. Murray, Jr. , Scott W. Smith , Wayne A. Perzan
发明人： Thomas O. Holtey , Thomas L. Murray, Jr. , Scott W. Smith , Wayne A. Perzan
IPC分类号： G06F13/10 , H04L29/06
CPC分类号： G06F13/10 , H04L29/06
摘要： A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit. These control elements are interconnected to the interface control unit and to the interface memory so that the multi-line communications unit is able to access different ones of the control locations for updating the status of the lines and further enabling the microprocessor-controlled interface control unit to transfer data to and from the transmit data and receive data locations of the lines in the predetermined sequence consistent with the status.
摘要翻译：一种通信控制器接口，用于仿真先前系统，采用多个发送和接收数据的线路单元。接口包括微处理器控制的接口控制单元，其具有具有多个可寻址存储位置的接口存储器。通过将接口存储器划分成与通信线路数量相对应的多个位置组，将每组位置细分为另外的位置，包括用于存储接收数据的位置，用于存储发送数据的位置，以及控制位置。存在多个控制元件，用于生成用于由接口控制单元执行的不同任务的信号序列。这些控制元件互连到接口控制单元和接口存储器，使得多线通信单元能够访问不同的控制位置以更新线路的状态，并且进一步启用微处理器控制的接口控制单元将数据传输到发送数据和从发送数据传送数据，并以与状态一致的预定顺序接收线路的数据位置。

2. 发明授权

US4965721A Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication 失效
标题翻译：用于控制包括多个数据通信线路中的测试操作的处理排序的固件状态设备
公开(公告)号：US4965721A
公开(公告)日：1990-10-23
申请号：US32896
申请日：1987-03-31
申请人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
发明人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
IPC分类号： G06F9/46 , G06F13/00 , G06F13/12 , H04Q3/545
CPC分类号： G06F13/124 , H04Q3/54583
摘要： A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications system and computer system. At least one processor having a program counter is employed for control data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor. The processor, in response to the group of instructions, performs a designated operation for the line and in particular in response to the test instruction loads a new value corresponding to the starting instruction of the group of instructions of the next state.

3. 发明授权

US4979104A Dual microprocessor control system 失效
标题翻译：双微处理器控制系统
公开(公告)号：US4979104A
公开(公告)日：1990-12-18
申请号：US32902
申请日：1987-03-31
申请人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
发明人： Thomas O. Holtey , Thomas L. Murray, Jr. , Wayne A. Perzan , Scott W. Smith
IPC分类号： G06F15/16 , G06F13/00 , G06F13/12 , G06F15/167 , H04L29/02
CPC分类号： G06F15/167 , G06F13/124
摘要： A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an incrementing manner while the other accesses in decrementing manner. When one microprocessor gains access to a specific line table excludes the other microprocessor from accessing that line table until the first microprocessor suspends off of that line table.

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