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1. 发明申请

US20060044909A1 Method and system for reducing the peak current in refreshing dynamic random access memory devices 有权
标题翻译：刷新动态随机存取存储器件中降低峰值电流的方法和系统
公开(公告)号：US20060044909A1
公开(公告)日：2006-03-02
申请号：US10931564
申请日：2004-08-31
申请人： Thomas Kinsley , Jeffery Janzen
发明人： Thomas Kinsley , Jeffery Janzen
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.
摘要翻译：动态随机存取存储器件包括用延迟值编程的模式寄存器。在一些实施例中，偏移代码也存储在存储器件中。存储器件使用延迟值，该延迟值可以被添加到偏移代码或乘以偏移代码，以延迟接收的自动刷新或自刷新命令的启动。可以为系统中的大量动态随机存取存储器件提供不同的延迟值和可能的偏移代码，使得存储器件不是都响应于自动刷新或自刷新命令而同时执行刷新同时存储设备。结果，由自动刷新命令或自刷新命令产生的存储器件所绘制的峰值电流保持在较低的值。

2. 发明申请

US20060221748A1 Method and system for reducing the peak current in refreshing dynamic random access memory devices 失效
公开(公告)号：US20060221748A1
公开(公告)日：2006-10-05
申请号：US11431371
申请日：2006-05-09
申请人： Thomas Kinsley , Jeffery Janzen
发明人： Thomas Kinsley , Jeffery Janzen
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.

3. 发明申请

US20070210447A1 Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems and methods 有权
标题翻译：用于将电子部件和基板固定在一起的细长紧固件，包括这种紧固件的半导体器件组件以及伴随的系统和方法
公开(公告)号：US20070210447A1
公开(公告)日：2007-09-13
申请号：US11369571
申请日：2006-03-07
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L24/72 , H01L25/0652 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06558 , H01L2225/06562 , H01L2225/06582 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H05K3/325 , H05K2201/10598 , H05K2201/10719 , H01L2924/00
摘要： Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.
摘要翻译：半导体器件组件包括诸如电子部件的元件和通过紧固件固定在一起的基板，该紧固件包括连续延伸穿过两个或更多个这样的元件中的孔的细长部分。计算机系统包括这样的半导体器件组件。用于将这些元件固定在一起的紧固件包括细长部分，第一端部件和第二端部件。将多个半导体器件固定在一起的方法包括通过第一半导体器件中的孔和至少一个附加半导体器件中的孔插入紧固件的细长部分。电路板包括与半导体器件组件中的孔阵列对应设置的多个孔。每个孔的尺寸和构造被设计成接收用于维持半导体器件组件和电路板之间的组装关系的紧固件。

4. 发明授权

US08590146B2 Connection verification technique 有权
标题翻译：连接验证技术
公开(公告)号：US08590146B2
公开(公告)日：2013-11-26
申请号：US12938208
申请日：2010-11-02
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： H05K3/34 , H05K3/20 , H05K3/30
CPC分类号： B23K1/0016 , G01R31/048 , H05K1/0268 , H05K1/111 , H05K3/3436 , H05K2201/09663 , H05K2201/09809 , H05K2201/10734 , H05K2203/163 , H05K2203/175 , Y02P70/611 , Y10T29/49004 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144
摘要： A method comprising coupling a device to a printed circuit board, one of the device or the printed circuit board having a first connection pad and a second connection pad. The first and second connection pads are directly electrically coupled to one another, without any intervening components between the first and second connection pads, via a test path. The method further comprises performing a continuity test across the first and second connection pads and the test path and disabling the test path between the first and second connection pads.
摘要翻译：一种方法，包括将装置耦合到印刷电路板，所述装置或印刷电路板中的一个具有第一连接焊盘和第二连接焊盘。第一和第二连接焊盘通过测试路径彼此直接电耦合，而在第一和第二连接焊盘之间没有任何中间部件。该方法还包括跨越第一和第二连接焊盘和测试路径执行连续性测试，并禁用第一和第二连接焊盘之间的测试路径。

5. 发明授权

US07835158B2 Connection verification technique 有权
标题翻译：连接验证技术
公开(公告)号：US07835158B2
公开(公告)日：2010-11-16
申请号：US11323757
申请日：2005-12-30
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： H05K1/18
CPC分类号： B23K1/0016 , G01R31/048 , H05K1/0268 , H05K1/111 , H05K3/3436 , H05K2201/09663 , H05K2201/09809 , H05K2201/10734 , H05K2203/163 , H05K2203/175 , Y02P70/611 , Y10T29/49004 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144
摘要： Embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed.
摘要翻译：本发明的实施例一般涉及测试存储器件与电路板或其他器件的连接。在一个实施例中，公开了一种被配置为便于该设备与印刷电路板或其他设备之间的连续性测试的存储器件。存储器件包括一个基片和两个通过测试路径彼此电耦合的连接焊盘。还公开了一种用于测试存储器件和电路板或其它器件之间的连接的系统和方法。

6. 发明申请

US20060198178A1 Memory stacking system and method 有权
标题翻译：内存堆叠系统和方法
公开(公告)号：US20060198178A1
公开(公告)日：2006-09-07
申请号：US11413793
申请日：2006-04-28
申请人： Thomas Kinsley , Kevin Kilbuck
发明人： Thomas Kinsley , Kevin Kilbuck
IPC分类号： G11C5/00
CPC分类号： G11C5/04 , G11C5/02 , G11C8/12
摘要： A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.
摘要翻译：提供了一种从多个存储器件形成堆叠的存储器模块的方法。多个存储器件中的每一个被修改为包括用于解码多个芯片选择信号的逻辑块。还提供了包括经修改的存储器件和串行存在检测器件的第一高密度存储器模块。第一高密度存储器模块被包括在电子系统内。此外，提供了形成堆叠存储器模块的附加方法，该方法需要修改地址缓冲器以包括用于解码多个片选信号的逻辑块。还提供了第二高密度存储器模块，其包括修改的地址缓冲器和串行存在检测器件。第二高密度存储器模块包括在电子系统内。

7. 发明申请

US20070152692A1 Connection verification technique 有权
标题翻译：连接验证技术
公开(公告)号：US20070152692A1
公开(公告)日：2007-07-05
申请号：US11323757
申请日：2005-12-30
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： G01R31/02
CPC分类号： B23K1/0016 , G01R31/048 , H05K1/0268 , H05K1/111 , H05K3/3436 , H05K2201/09663 , H05K2201/09809 , H05K2201/10734 , H05K2203/163 , H05K2203/175 , Y02P70/611 , Y10T29/49004 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144
摘要： Embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed.
摘要翻译：本发明的实施例一般涉及测试存储器件与电路板或其他器件的连接。在一个实施例中，公开了一种被配置为便于该设备与印刷电路板或其他设备之间的连续性测试的存储器件。存储器件包括一个基片和两个通过测试路径彼此电耦合的连接焊盘。还公开了一种用于测试存储器件和电路板或其它器件之间的连接的系统和方法。

8. 发明申请

US20070093139A1 Edge connector including internal layer contact, printed circuit board and electronic module incorporating same 有权
标题翻译：边缘连接器包括内层接触，印刷电路板和并入其的电子模块
公开(公告)号：US20070093139A1
公开(公告)日：2007-04-26
申请号：US11642346
申请日：2006-12-20
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： H01R24/00
CPC分类号： H05K1/117 , H01R12/58 , H01R12/7076 , H01R12/721 , H01R2201/06 , H05K1/0298 , H05K3/403 , H05K2201/0919 , H05K2201/09845 , H05K2203/1572
摘要： An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first major exterior surface, a second major exterior surface, and a minor exterior surface. The edge connector further includes at least one of a first conductive contact affixed to the first major exterior surface and one of a second conductive contact affixed to the second major exterior surface. Additionally, the edge connector includes at least one third conductive contact conductively coupled to at least a portion of any internal conductive layer of the substrate and the third conductive contact is configured off-plane from the minor exterior surface.
摘要翻译：描述了边缘连接器，系统，印刷电路板和电子模块，其包括由包括第一主外表面，第二主外表面和次外表面的基板组成的边缘连接器。边缘连接器还包括固定到第一主外表面的第一导电触头和固定到第二主外表面的第二导电触头中的至少一个。另外，边缘连接器包括导电地耦合到衬底的任何内部导电层的至少一部分的至少一个第三导电接触件，并且第三导电接触件被构造成离开次要外表面。

9. 发明申请

US20110041317A1 CONNECTION VERIFICATION TECHNIQUE 有权
标题翻译：连接验证技术
公开(公告)号：US20110041317A1
公开(公告)日：2011-02-24
申请号：US12938208
申请日：2010-11-02
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： B23K31/02 , G01R31/28
CPC分类号： B23K1/0016 , G01R31/048 , H05K1/0268 , H05K1/111 , H05K3/3436 , H05K2201/09663 , H05K2201/09809 , H05K2201/10734 , H05K2203/163 , H05K2203/175 , Y02P70/611 , Y10T29/49004 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144
摘要： Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.
摘要翻译：本发明的一些实施例通常涉及测试存储器件与电路板或其它器件的连接。在一个实施例中，公开了一种被配置为便于该设备与印刷电路板或其他设备之间的连续性测试的存储器件。存储器件包括一个基片和两个通过测试路径彼此电耦合的连接焊盘。还公开了用于测试存储器件和电路板或其他器件之间的连接的系统和方法，以及用于检测过温度并使得能够使用多级连接焊盘的特殊功能的附加技术。

10. 发明申请

US20060189175A1 EDGE CONNECTOR INCLUDING INTERNAL LAYER CONTACT, PRINTED CIRCUIT BOARD AND ELECTRONIC MODULE INCORPORATING SAME 有权
标题翻译：边缘连接器，包括内层接触器，印刷电路板和与之同步的电子模块
公开(公告)号：US20060189175A1
公开(公告)日：2006-08-24
申请号：US11064344
申请日：2005-02-22
申请人： Thomas Kinsley
发明人： Thomas Kinsley
IPC分类号： H01R12/00
CPC分类号： H05K1/117 , H01R12/58 , H01R12/7076 , H01R12/721 , H01R2201/06 , H05K1/0298 , H05K3/403 , H05K2201/0919 , H05K2201/09845 , H05K2203/1572
摘要： An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first major exterior surface, a second major exterior surface, and a minor exterior surface. The edge connector further includes at least one of a first conductive contact affixed to the first major exterior surface and one of a second conductive contact affixed to the second major exterior surface. Additionally, the edge connector includes at least one third conductive contact conductively coupled to at least a portion of any internal conductive layer of the substrate and the third conductive contact is configured off-plane from the minor exterior surface.
摘要翻译：描述了边缘连接器，系统，印刷电路板和电子模块，其包括由包括第一主外表面，第二主外表面和次外表面的基板组成的边缘连接器。边缘连接器还包括固定到第一主外表面的第一导电触头和固定到第二主外表面的第二导电触头中的至少一个。另外，边缘连接器包括导电地耦合到衬底的任何内部导电层的至少一部分的至少一个第三导电接触件，并且第三导电接触件被构造成离开次要外表面。

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