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    • 4. 发明授权
    • Cache pollution avoidance instructions
    • 缓存污染回避说明
    • US06275904B1
    • 2001-08-14
    • US09053385
    • 1998-03-31
    • Srinivas ChennupatyShreekant S. ThakkarThomas HuffVladimir Pentkovski
    • Srinivas ChennupatyShreekant S. ThakkarThomas HuffVladimir Pentkovski
    • G06F1208
    • G06F12/0886G06F9/30018G06F9/30036G06F9/30047G06F12/0804G06F12/0888
    • A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
    • 一种用于提供高速缓存存储器管理的计算机系统和方法。 计算机系统包括具有多个主存储器地址的主存储器,每个主存储器地址都具有对应的数据条目,以及耦合到主存储器的处理器。 至少一个高速缓存存储器耦合到处理器。 所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。 处理器接收具有操作数地址的指令,并确定操作数地址是否匹配高速缓存目录中的多个地址之一。 如果是这样,则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。 否则,更新与主存储器中的操作数地址相对应的数据条目。
    • 6. 发明授权
    • System and method for performing an intra-add operation
    • 用于执行加入内操作的系统和方法
    • US06211892B1
    • 2001-04-03
    • US09053389
    • 1998-03-31
    • Thomas HuffShreekant S. Thakkar
    • Thomas HuffShreekant S. Thakkar
    • G06T1522
    • G06T15/005
    • An apparatus and method for performing an intra-add operation on packed data using computer-implemented steps is described. A processor is coupled to a hardware unit which transmits data representing graphics to another computer or display. A storage device coupled to the processor, has stored therein a routine, which, when executed by the processor, causes the processor to generate the data. The routine causes the processor to at least access a first packed data operand having at least one pair of data elements; swap positions of the data elements within the at least one pair of data elements to generate a second packed data operand, add data elements starting at the same bit positions from the first and second packed data operands to generate a third packed data operand.
    • 描述了使用计算机实现的步骤对打包数据执行加入内操作的装置和方法。 处理器耦合到将表示图形的数据传送到另一计算机或显示器的硬件单元。 耦合到处理器的存储设备,其中存储有例程,当由处理器执行时,处理器产生数据。 该例程使处理器至少访问具有至少一对数据元素的第一打包数据操作数; 在所述至少一对数据元素内的所述数据元素的交换位置以产生第二打包数据操作数,从所述第一和第二打包数据操作数添加从相同位位置开始的数据元素,以生成第三打包数据操作数。