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1. 发明授权

US07415569B2 Memory including a write training block 有权
标题翻译：内存包括一个写入训练块
公开(公告)号：US07415569B2
公开(公告)日：2008-08-19
申请号：US11386360
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F12/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器和写入训练块。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移动FIFO输出指针的信息。

2. 发明授权

US07457913B2 Finding a data pattern in a memory 有权
标题翻译：在内存中查找数据模式
公开(公告)号：US07457913B2
公开(公告)日：2008-11-25
申请号：US11386176
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G11C7/1006 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C15/04
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和多路复用器。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移位FIFO输出指针的信息。多路复用器用于从输出指针计数器接收FIFO输出指针的值。复用器还用于接收用于移位FIFO输出指针的复用信息。复用器还用于基于复用信息来移位FIFO输出指针的值。

3. 发明申请

US20070226429A1 Memory including a write training block 有权
标题翻译：内存包括一个写入训练块
公开(公告)号：US20070226429A1
公开(公告)日：2007-09-27
申请号：US11386360
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器和写入训练块。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移动FIFO输出指针的信息。

4. 发明申请

US20070245096A1 Finding a data pattern in a memory 有权
标题翻译：在内存中查找数据模式
公开(公告)号：US20070245096A1
公开(公告)日：2007-10-18
申请号：US11386176
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F13/00
CPC分类号： G06F13/1689 , G11C7/1006 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C15/04
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和多路复用器。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移位FIFO输出指针的信息。多路复用器用于从输出指针计数器接收FIFO输出指针的值。复用器还用于接收用于移位FIFO输出指针的复用信息。复用器还用于基于复用信息来移位FIFO输出指针的值。

5. 发明授权

US07792037B2 Integrated circuit including data synchronization apparatus and method 有权
标题翻译：集成电路包括数据同步装置和方法
公开(公告)号：US07792037B2
公开(公告)日：2010-09-07
申请号：US11924031
申请日：2007-10-25
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G08C15/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4096 , G11C2207/107
摘要： A synchronization apparatus for data synchronization and method for data synchronization is disclosed. One embodiment provides clock signals which are phase-shifted relative to one another are used for synchronizing data packets in a serial-to-parallel conversion device in a write path and equally for synchronizing data packets in a parallel-to-serial conversion device in a read path.
摘要翻译：公开了一种用于数据同步的同步装置和用于数据同步的方法。一个实施例提供相对于彼此相移的时钟信号用于同步写入路径中的串行 - 并行转换装置中的数据分组，并且同样用于在并行到串行转换装置中同步数据分组读路径

6. 发明申请

US20080101238A1 INTEGRATED CIRCUIT INCLUDING DATA SYNCHRONIZATION APPARATUS AND METHOD 有权
标题翻译：集成电路，包括数据同步装置和方法
公开(公告)号：US20080101238A1
公开(公告)日：2008-05-01
申请号：US11924031
申请日：2007-10-25
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G08C15/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4096 , G11C2207/107
摘要： A synchronization apparatus for data synchronization and method for data synchronization is disclosed. One embodiment provides clock signals which are phase-shifted relative to one another are used for synchronizing data packets in a serial-to-parallel conversion device in a write path and equally for synchronizing data packets in a parallel-to-serial conversion device in a read path.
摘要翻译：公开了一种用于数据同步的同步装置和用于数据同步的方法。一个实施例提供相对于彼此相移的时钟信号用于同步写入路径中的串行 - 并行转换装置中的数据分组，并且同样用于在并行到串行转换装置中同步数据分组读路径

7. 发明授权

US07848134B2 FB DRAM memory with state memory 有权
标题翻译： FB DRAM内存带状态存储器
公开(公告)号：US07848134B2
公开(公告)日：2010-12-07
申请号：US12178407
申请日：2008-07-23
申请人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
发明人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/404 , G11C2211/4016
摘要： A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.
摘要翻译：公开了具有耦合到第一FB DRAM单元和第二FB DRAM单元的字线的具有多个FB DRAM单元的存储器芯片。存储器芯片还具有耦合到第一FB DRAM单元的第一位线和耦合到第一位线的第一状态存储器电路。存储器芯片还包括耦合到第二FB DRAM单元的第二位线和耦合到第二位线的第二状态存储器电路。存储器芯片还包括读出放大器，其可耦合到第一FB DRAM单元，第二FB DRAM单元，第一状态存储器电路或第二状态存储器电路。

8. 发明授权

US07797042B2 Device for applying a transcutaneous stimulus or for transcutaneous measuring of a parameter 有权
标题翻译：用于施用经皮刺激或经皮测量参数的装置
公开(公告)号：US07797042B2
公开(公告)日：2010-09-14
申请号：US11750495
申请日：2007-05-18
申请人： Stefan Dietrich , Timo Freitag
发明人： Stefan Dietrich , Timo Freitag
IPC分类号： A61N1/18
CPC分类号： A61H39/002 , A61H21/00 , A61H2201/1645 , A61H2205/027 , A61N1/0456 , A61N1/0541 , A61N1/32 , A61N1/36014 , A61N1/36036
摘要： The apparatus for transcutaneous stimulation or transcutaneous measurement of a parameter is a device which fits wholly within the pinna (external ear) of the vertebrate. In order to fit completely within the pinna, the housing is C-shaped and from each end of the housing is a curved section which has a spring action that holds the apparatus inside the ear. This apparatus has a compact design which allows for nerve stimulation in a particularly efficient, ergonomically favorable and easy manipulation for the patient.
摘要翻译：用于经皮刺激或经皮测量参数的装置是完全适合脊椎动物的针刺（外耳）的装置。为了完全配合在针刺内，壳体是C形的，并且从壳体的每个端部是弯曲部分，其具有将装置保持在耳朵内部的弹簧作用。该装置具有紧凑的设计，其能够以对患者特别有效的，符合人体工程学的有利且容易的操作来进行神经刺激。

9. 发明授权

US07633814B2 Memory device and method of operating such 失效
标题翻译：内存设备及操作方法
公开(公告)号：US07633814B2
公开(公告)日：2009-12-15
申请号：US11735928
申请日：2007-04-16
申请人： Paul Wallner , Stefan Dietrich , Peter Gregorius
发明人： Paul Wallner , Stefan Dietrich , Peter Gregorius
IPC分类号： G11C16/04
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.
摘要翻译：一种存储器件，包括存储单元阵列; 用于接收命令数据并向存储单元阵列提供驱动信号的输入电路; 用于缓冲从存储单元阵列读出的数据的输出缓冲器; 以及用于驱动输出缓冲器的定时器，使得在经过预定时间间隔之后的输出处提供缓冲数据，从提供驱动信号开始的预定时间间隔。

10. 发明申请

US20090219529A1 METHOD AND APPARATUS FOR DETERMINING THE PARTICLES CONTAINED IN A PARTICLE STREAM 有权
标题翻译：用于测定颗粒物流中颗粒的方法和装置
公开(公告)号：US20090219529A1
公开(公告)日：2009-09-03
申请号：US12299744
申请日：2007-04-30
申请人： Stefan Dietrich , Guenter Eckardt , Michael Koehler
发明人： Stefan Dietrich , Guenter Eckardt , Michael Koehler
IPC分类号： G01N15/02
CPC分类号： G06M1/101 , G01N15/1429 , G01N15/1459 , G01N2015/1075 , G01N2015/1402
摘要： A method and an apparatus for determining the particle content of a particle stream using a source of light and two receivers arranged offset from one another in the flow direction of the particle stream. The receivers provide an electrical signal to an evaluation unit as a function of the radiation intensity which they receive, and this signal makes possible a determination of the flow velocity and particle size. Coincident passage of two particles is indicated by a pulse occurring in the signal due to a “roof collapse” in the pulse caused by a weakening of the radiation intensity as the particles pass a receiver.
摘要翻译：一种用于使用光源确定颗粒物流的颗粒含量的方法和装置，以及在颗粒物流的流动方向彼此偏移地设置的两个接收器。接收器根据接收到的辐射强度向评估单元提供电信号，并且该信号使流动速度和粒度的确定成为可能。两个颗粒的重合通道由信号中出现的脉冲表示，这是由于当颗粒通过接收器时由辐射强度减弱引起的脉冲中的“屋顶塌陷”。

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