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1. 发明授权

US06956390B1 Method and apparatus for verifying temperature during integrated circuit thermal testing 有权
标题翻译：集成电路热测试期间验证温度的方法和装置
公开(公告)号：US06956390B1
公开(公告)日：2005-10-18
申请号：US10651779
申请日：2003-08-29
申请人： Thomas A. Feltner , James S. Aylett , John C. Marley , Thomas A. Gallagher
发明人： Thomas A. Feltner , James S. Aylett , John C. Marley , Thomas A. Gallagher
IPC分类号： G01R1/04 , G01R31/02 , G01R31/26
CPC分类号： G01R1/0458
摘要： An test block includes a box-like body and four rails extending from side edges of the body. During thermal testing, the test block is mounted between a test head and a test socket such that the rails provide a thermal path between the test block body and contact pads formed on the test socket. In this manner the rails emulate the thermal path formed by the metal leads extending from a conventional Quad Flat Pack Integrated Circuit (QFP IC), thereby reliably duplicating the actual thermal path of the QFP IC. The test block is mounted on the test system and its temperature is measured before and after testing QFP IC devices. Confirming that the test block is within test temperature specifications before and after the QFP-IC test procedure provides a highly reliable verification that the QFP-IC's actual test temperature is within the test temperature specifications.
摘要翻译：测试块包括一个盒状体和四个从身体的侧边缘延伸的轨道。在热测试期间，测试块安装在测试头和测试插座之间，使得轨道在测试块体和测试插座上形成的接触垫之间提供热路径。以这种方式，轨道模拟由传统的Quad Flat Pack集成电路（QFP IC）延伸的金属引线形成的热路径，从而可靠地复制QFP IC的实际热路径。测试块安装在测试系统上，测试QFP IC器件前后的温度。在QFP-IC测试程序之前和之后确认测试块在测试温度规格范围内，提供了QFP-IC实际测试温度在测试温度规格内的高可靠性验证。

2. 发明授权

US06457251B1 Method and apparatus for calibrating device pick-up heads used in integrated circuit handler systems 有权
标题翻译：用于校准集成电路处理器系统中使用的装置拾取头的方法和装置
公开(公告)号：US06457251B1
公开(公告)日：2002-10-01
申请号：US09652386
申请日：2000-08-31
申请人： Thomas A. Feltner , John C. Marley
发明人： Thomas A. Feltner , John C. Marley
IPC分类号： G01B330
CPC分类号： H05K13/08 , H05K13/0413 , H05K13/089
摘要： A calibration assembly and method for calibrating the device pick-up heads used in multi-head IC handlers such that all of the device pick-up heads are reliably calibrated to a consistent optimal calibration position. Gauge blocks are provided that greatly simplify the calibration process by holding the movable portion of a device pick-up head in an optimal calibration position relative to the base structure of the device pick-up head while the collar is secured. Each gauge block has base portion for supporting the base structure of the device pick-up head, and a flat contact surface against which the lower surface of the movable portion is pressed. The contact surface is a predetermined distance from the base portion such that when the device pick-up head is mounted on the gauge block, the movable portion is maintained in an optimal calibration position relative to the base structure.
摘要翻译：一种用于校准用于多头IC处理器中的装置拾取头的校准组件和方法，使得所有的装置拾取头可靠地校准到一致的最佳校准位置。提供了测量块，其通过将装置拾取头的可移动部分相对于装置拾取头的基部结构保持在最佳校准位置而极大地简化了校准过程，而套环被固定。每个量规块具有用于支撑装置拾取头的基部结构的基部和平面接触表面，可动部的下表面与该平面接触表面被按压。接触表面距离基部预定距离，使得当装置拾取头安装在量块上时，可移动部分相对于基部结构保持在最佳的校准位置。

3. 发明授权

US06978541B1 Apparatus and methods to enhance thermal energy transfer in IC handler systems 有权
标题翻译：在IC处理系统中增强热能传递的装置和方法
公开(公告)号：US06978541B1
公开(公告)日：2005-12-27
申请号：US10262998
申请日：2002-10-01
申请人： Thomas A. Feltner , John C. Marley
发明人： Thomas A. Feltner , John C. Marley
IPC分类号： H05K13/04 , H01L3/34
CPC分类号： H05K13/0465 , H05K13/0409 , Y10T29/49144
摘要： Disclosed is apparatus to enhance thermal energy transfer from a heater to a DUT in IC handler systems. The pick-up head of an IC handler system is made of metal blocks in maximal thermal contact, and further includes an electrically resistive and thermally conductive layer. The electrically resistive layer provides ESD protection to the DUT. The preferred apparatus uses a collapsible billows suction cup to secure, pick-up, and align DUTs.
摘要翻译：公开了在IC处理器系统中增强从加热器到DUT的热能传递的装置。 IC处理器系统的拾取头由最大热接触的金属块制成，并且还包括电阻和导热层。电阻层向DUT提供ESD保护。优选的装置使用可折叠的枕式吸盘来固定，拾取和对准DUT。

4. 发明授权

US06856862B1 Light curtain safety system for semiconductor device handler 有权
标题翻译：半导体器件处理器的光幕安全系统
公开(公告)号：US06856862B1
公开(公告)日：2005-02-15
申请号：US10391821
申请日：2003-03-18
申请人： Thomas A. Feltner
发明人： Thomas A. Feltner
IPC分类号： F16P3/14 , G01V8/20 , G05B19/00
CPC分类号： F16P3/144 , G01V8/20 , H01L21/67253 , H01L21/67259 , H01L21/67288
摘要： A light curtain safety system for a semiconductor device handler that includes a programmable control unit and a robot mechanism that is selectively operated in response to signals generated by the control unit. The light curtain safety system includes an apparatus for generating a light curtain such that accessing the robot mechanism requires breaking the light curtain. The light curtain safety system detects an operating state of the semiconductor device handler using signals generated in the control unit, and allows de-activation of the light curtain apparatus only when operating state of the semiconductor device handler is in a predetermined “safe” operating state. When the light curtain apparatus is active and the light curtain is broken, the light curtain safety system causes the semiconductor device handler to terminate power flow to the robot mechanism.
摘要翻译：一种用于半导体器件处理器的光幕安全系统，其包括可编程控制单元和机械手机构，所述可编程控制单元和机器人机构响应于由所述控制单元产生的信号选择性地操作。光幕安全系统包括用于产生光幕的装置，使得接近机器人机构需要破坏光幕。光幕安全系统使用在控制单元中产生的信号来检测半导体器件处理器的操作状态，并且仅当半导体器件处理器的操作状态处于预定的“安全”操作状态时才允许光幕设备的去激活。当光幕装置处于活动状态并且光幕破裂时，光幕安全系统使得半导体装置处理器终止到机器人机构的电力流动。

5. 发明授权

US06703852B1 Low-temperature semiconductor device testing apparatus with purge box 失效
标题翻译：带清洗箱的低温半导体器件检测仪器
公开(公告)号：US06703852B1
公开(公告)日：2004-03-09
申请号：US10323962
申请日：2002-12-18
申请人： Thomas A. Feltner
发明人： Thomas A. Feltner
IPC分类号： G01R3102
CPC分类号： G01R1/0458
摘要： A low-temperature semiconductor device test apparatus that includes a device tester having a purge box mounted thereon, a low-temperature handler system, and a load board having a IC test socket. The purge box is located between the load board and a support plate of the device tester, and between groups of compressible test pins used to pass test signals to the test socket through conductive traces formed in the load board. The purge box includes rigid outer walls defining a chamber that is located opposite to the test sockets. During low-temperature testing, dry air is pumped into the chamber through conduits formed in the walls of the purge box to prevent the condensation of moisture on conductors formed on the load board and exposed in the chamber. In addition, the purge box resists bending of the load board when semiconductor devices are pressed against the test sockets.
摘要翻译：一种低温半导体器件测试装置，包括其上安装有净化箱的设备测试器，低温处理器系统和具有IC测试插座的负载板。净化箱位于装载板和装置测试仪的支撑板之间，以及用于通过形成在装载板上的导电迹线将测试信号传递到测试插座的可压缩测试针组之间。净化箱包括限定与测试插座相对定位的室的刚性外壁。在低温试验期间，干燥空气通过形成在清除箱壁上的导管泵入室内，以防止在形成在负载板上并暴露在室中的导体上的水分冷凝。此外，当半导体器件压靠在测试插座上时，清除盒抵抗负载板的弯曲。

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