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1. 发明申请

US20120196425A1 High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials 审中-公开
标题翻译：基于占位符材料优越平面度的替代门法形成的高K金属栅电极结构
公开(公告)号：US20120196425A1
公开(公告)日：2012-08-02
申请号：US13354613
申请日：2012-01-20
申请人： Thilo Scheiper , Andy Wei , Stefan Flachowsky , Jan Hoentschel
发明人： Thilo Scheiper , Andy Wei , Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L29/785 , H01L21/823828 , H01L29/513 , H01L29/66545 , H01L29/66795
摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures.
摘要翻译：当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过在诸如多晶硅材料的占位符材料的沉积之后实施至少一个平坦化工艺，并且在实际上图案化栅电极结构。

2. 发明申请

US20130071977A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS 有权
标题翻译：用于制造具有门到集成电路的主动和门来互连的方法
公开(公告)号：US20130071977A1
公开(公告)日：2013-03-21
申请号：US13237688
申请日：2011-09-20
申请人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
发明人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/76895 , H01L21/76897
摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
摘要翻译：提供了用于制造包括门到活动触点的集成电路的方法。一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。填充层被平坦化以暴露伪栅极并且去除虚拟栅极。形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。

3. 发明授权

US08722500B2 Methods for fabricating integrated circuits having gate to active and gate to gate interconnects 有权
标题翻译：用于制造具有栅极到栅极到栅极互连的集成电路的方法
公开(公告)号：US08722500B2
公开(公告)日：2014-05-13
申请号：US13237688
申请日：2011-09-20
申请人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
发明人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/76895 , H01L21/76897
摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
摘要翻译：提供了用于制造包括门到活动触点的集成电路的方法。一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。填充层被平坦化以暴露伪栅极并且去除虚拟栅极。形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。

4. 发明授权

US08404550B2 Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
标题翻译：通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强
公开(公告)号：US08404550B2
公开(公告)日：2013-03-26
申请号：US12905383
申请日：2010-10-15
申请人： Thilo Scheiper , Sven Beyer , Andy Wei , Jan Hoentschel
发明人： Thilo Scheiper , Sven Beyer , Andy Wei , Jan Hoentschel
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66651
摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.
摘要翻译：在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如在形成阈值调节半导体材料之前。因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险事件

5. 发明申请

US20110266633A1 Semiconductor Device Comprising Metal Gates and Semiconductor Resistors Formed on the Basis of a Replacement Gate Approach 有权
标题翻译：包括金属栅极和半导体电阻的半导体器件以替代栅极方式形成
公开(公告)号：US20110266633A1
公开(公告)日：2011-11-03
申请号：US12963364
申请日：2010-12-08
申请人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
发明人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L23/5252 , H01L23/5256 , H01L27/0629 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.
摘要翻译：在替代栅极方法中，可以在更换栅电极结构中的半导体材料时保留半导体材料或其非晶体管结构中的至少其重要部分，例如精密电阻器，电子熔丝等。为此，可以至少在去除栅电极结构中的半导体材料之前提供适当的介电材料，而不需要对建立的替代栅极方法进行显着的修改。

6. 发明授权

US08450163B2 Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach 有权
标题翻译：半导体器件包括基于替代栅极方法形成的金属栅极和半导体电阻器
公开(公告)号：US08450163B2
公开(公告)日：2013-05-28
申请号：US12963364
申请日：2010-12-08
申请人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
发明人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L21/338 , H01L21/20 , H01L21/337 , H01L23/62
CPC分类号： H01L23/5252 , H01L23/5256 , H01L27/0629 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.
摘要翻译：在替代栅极方法中，可以在更换栅电极结构中的半导体材料时保留半导体材料或其非晶体管结构中的至少其重要部分，例如精密电阻器，电子熔丝等。为此，可以至少在去除栅电极结构中的半导体材料之前提供适当的介电材料，而不需要对建立的替代栅极方法进行显着的修改。

7. 发明授权

US08026134B2 Recessed drain and source areas in combination with advanced silicide formation in transistors 有权
标题翻译：嵌入式漏极和源极区域与晶体管中先进的硅化物形成相结合
公开(公告)号：US08026134B2
公开(公告)日：2011-09-27
申请号：US12549769
申请日：2009-08-28
申请人： Uwe Griebenow , Andy Wei , Jan Hoentschel , Thilo Scheiper
发明人： Uwe Griebenow , Andy Wei , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/30608 , H01L21/32134 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.
摘要翻译：在用于形成复杂的晶体管元件的制造过程中，栅极高度可以减小，并且在形成相应的金属硅化物区域之前可以在公共蚀刻序列中获得凹陷的漏极和源极配置。由于可以在蚀刻顺序期间保持相应的侧壁间隔结构，所以可以提高栅电极中的硅化处理的可控性和均匀性，从而获得阈值变化程度的降低。此外，凹陷的漏极和源极配置可以提供减小的整体串联电阻和增强的应力传递效率。

8. 发明申请

US20110159657A1 ENHANCED INTEGRITY OF A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL SPACER FOR CAP REMOVAL 有权
标题翻译：通过使用真空间隔器去除高K金属电极结构的增强的完整性
公开(公告)号：US20110159657A1
公开(公告)日：2011-06-30
申请号：US12907675
申请日：2010-10-19
申请人： Uwe Griebenow , Jan Hoentschel , Thilo Scheiper , Andy Wei
发明人： Uwe Griebenow , Jan Hoentschel , Thilo Scheiper , Andy Wei
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall spacer structure, which may preserve integrity of sensitive gate materials and may also determine the lateral offset of a strain-inducing semiconductor material.
摘要翻译：在用于在早期制造阶段形成复杂的高k金属栅极电极结构的工艺策略中，介电盖材料可以基于保护性间隔元件去除，从而确保氮化硅侧壁间隔结构的完整性，其可以保持敏感栅极材料的完整性并且还可以确定应变诱导半导体材料的横向偏移。

9. 发明申请

US20110101427A1 TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT 审中-公开
标题翻译：基于超级植入掩蔽效应的晶体管，包括在排水/源区域形成的高K金属电极结构
公开(公告)号：US20110101427A1
公开(公告)日：2011-05-05
申请号：US12899080
申请日：2010-10-06
申请人： Thilo Scheiper , Andy Wei , Sven Beyer , Jan Hoentschel , Uwe Griebenow
发明人： Thilo Scheiper , Andy Wei , Sven Beyer , Jan Hoentschel , Uwe Griebenow
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/266 , H01L21/28247 , H01L21/823814 , H01L21/84 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： When forming a sophisticated high-k metal gate stack in an early manufacturing stage, the dielectric cap layer may be efficiently removed without unduly affecting the drain and source extension regions. To this end, a specifically designed sidewall spacer structure may be used, such as a silicon dioxide spacer element in combination with a silicon nitride etch stop liner. The spacer structure may thus enable the removal of the dielectric cap layer while still maintaining the functions of an implantation mask and a silicidation mask during the further processing.
摘要翻译：当在早期制造阶段中形成复杂的高k金属栅极堆叠时，可以有效地去除电介质盖层而不会不利地影响漏极和源极延伸区域。为此，可以使用特别设计的侧壁间隔结构，例如与氮化硅蚀刻停止衬垫组合的二氧化硅隔离元件。因此，间隔物结构可以在进一步处理期间能够移除电介质盖层同时保持注入掩模和硅化掩模的功能。

10. 发明申请

US20110186937A1 ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION 审中-公开
标题翻译：基于较晚的植被的晶体管特性的调整
公开(公告)号：US20110186937A1
公开(公告)日：2011-08-04
申请号：US12914343
申请日：2010-10-28
申请人： Thilo Scheiper , Sven Beyer , Jan Hoentschel , Andy Wei
发明人： Thilo Scheiper , Sven Beyer , Jan Hoentschel , Andy Wei
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/28088 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/105 , H01L29/1083 , H01L29/4966 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A self-aligned well implantation process may be performed so as to adjust threshold voltage and/or body resistance of transistors. To this end, after removing a placeholder material of gate electrode structures, the implantation process may be performed on the basis of appropriate process parameters to obtain the desired transistor characteristics. Thereafter, any appropriate electrode metal may be filled in, thereby providing gate electrode structures having superior performance. For example, high-k metal gate electrode structures may be formed on the basis of a replacement gate approach, while the additional late well implantation may provide a high degree of flexibility in providing different transistor versions of the same basic configuration.
摘要翻译：可以执行自对准阱注入工艺，以便调整晶体管的阈值电压和/或体电阻。为此，在去除栅电极结构的占位符材料之后，可以基于适当的工艺参数进行注入工艺以获得所需的晶体管特性。此后，可以填充任何合适的电极金属，从而提供具有优异性能的栅电极结构。例如，可以在替代栅极方法的基础上形成高k金属栅电极结构，而附加的后期阱注入可以提供相同基本配置的不同晶体管版本的高度灵活性。

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