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1. 发明授权

US08984254B2 Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance 有权
标题翻译：使用翻译后备缓冲区入口号来提高处理器性能的技术
公开(公告)号：US08984254B2
公开(公告)日：2015-03-17
申请号：US13630346
申请日：2012-09-28
申请人： Thang M. Tran , Edmund J. Gieske
发明人： Thang M. Tran , Edmund J. Gieske
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
摘要翻译：一种用于操作处理器的技术包括：通过翻译后备缓冲器中的第一入口号，使用关联的转换后备缓冲器将第一虚拟地址翻译成第一物理地址。该技术还包括通过翻译后备缓冲器中的第二入口号将翻译后备缓冲器翻译成第二虚拟地址转换为第二物理地址。该技术还包括响应于第一入口号与第二入口号相同，确定第一和第二虚拟地址指向存储器中相同的物理地址并引用相同的数据。

2. 发明申请

US20140095784A1 Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers to Improve Processor Performance 有权
标题翻译：利用事务后备缓冲区入口号来提高处理器性能的技术
公开(公告)号：US20140095784A1
公开(公告)日：2014-04-03
申请号：US13630346
申请日：2012-09-28
申请人： Thang M. Tran , Edmund J. Gieske
发明人： Thang M. Tran , Edmund J. Gieske
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A technique for operating a processor includes translating, using an associated transaction lookaside buffer, a first virtual address into a first physical address through a first entry number in the transaction lookaside buffer. The technique also includes translating, using the transaction lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
摘要翻译：用于操作处理器的技术包括通过事务后备缓冲器中的第一条目号码将使用相关联的事务后备缓冲器的第一虚拟地址翻译成第一物理地址。该技术还包括通过翻译后备缓冲器中的第二条目号码将使用事务后备缓冲器的第二虚拟地址翻译成第二物理地址。该技术还包括响应于第一入口号与第二入口号相同，确定第一和第二虚拟地址指向存储器中相同的物理地址并引用相同的数据。

3. 发明授权

US08458447B2 Branch target buffer addressing in a data processor 有权
标题翻译：在数据处理器中分支目标缓冲区寻址
公开(公告)号：US08458447B2
公开(公告)日：2013-06-04
申请号：US13162835
申请日：2011-06-17
申请人： Thang M. Tran , Edmund J. Gieske , Michael B. Schinzler
发明人： Thang M. Tran , Edmund J. Gieske , Michael B. Schinzler
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3806
摘要： A data processor includes a branch target buffer (BTB) having a plurality of BTB entries grouped in ways. The BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address.
摘要翻译：数据处理器包括具有以方式分组的多个BTB条目的分支目标缓冲器（BTB）。其中一种方式的BTB条目包括一个短标签地址，而另一种方式的BTB条目包括一个完整的标签地址。

4. 发明申请

US20120324209A1 BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR 有权
标题翻译：分支目标缓存器在数据处理器中寻址
公开(公告)号：US20120324209A1
公开(公告)日：2012-12-20
申请号：US13162835
申请日：2011-06-17
申请人： Thang M. Tran , Edmund J. Gieske , Michael B. Schinzler
发明人： Thang M. Tran , Edmund J. Gieske , Michael B. Schinzler
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： A data processor includes a branch target buffer (BTB) having a plurality of BTB entries grouped in ways. The BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address.
摘要翻译：数据处理器包括具有以方式分组的多个BTB条目的分支目标缓冲器（BTB）。其中一种方式的BTB条目包括一个短标签地址，而另一种方式的BTB条目包括一个完整的标签地址。

5. 发明申请

US20120233498A1 HIERARCHICAL ERROR CORRECTION FOR LARGE MEMORIES 有权
标题翻译：大型记忆体的分层错误校正
公开(公告)号：US20120233498A1
公开(公告)日：2012-09-13
申请号：US13045307
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
发明人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
摘要翻译：提供了一种用于检测和校正存储在正在读取的存储器区域中的数据段中的第一数量的位错误的机制，同时检测该数据段中是否存在较高数量的位错误。在存储器区域的任何单个数据段中检测到较高数量的位错误的情况下，对存储器区域执行该更高数量的位错误的错误校正，同时检测存在更高级别的位错误。通过以这样的分级顺序执行更高级别的比特错误的纠错，可以在大多数数据访问中避免与这种纠错相关联的存储器等待时间，从而提高数据访问的性能。

6. 发明授权

US08677205B2 Hierarchical error correction for large memories 有权
标题翻译：大存储器的分层纠错
公开(公告)号：US08677205B2
公开(公告)日：2014-03-18
申请号：US13045307
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
发明人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
摘要翻译：提供了一种用于检测和校正存储在正在读取的存储器区域中的数据段中的第一数量的位错误的机制，同时检测该数据段中是否存在较高数量的位错误。在存储器区域的任何单个数据段中检测到较高数量的位错误的情况下，对存储器区域执行该更高数量的位错误的错误校正，同时检测存在更高级别的位错误。通过以这样的分级顺序执行更高级别的比特错误的纠错，可以在大多数数据访问中避免与这种纠错相关联的存储器等待时间，从而提高数据访问的性能。

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