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1. 发明授权

US08677205B2 Hierarchical error correction for large memories 有权
标题翻译：大存储器的分层纠错
公开(公告)号：US08677205B2
公开(公告)日：2014-03-18
申请号：US13045307
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
发明人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
摘要翻译：提供了一种用于检测和校正存储在正在读取的存储器区域中的数据段中的第一数量的位错误的机制，同时检测该数据段中是否存在较高数量的位错误。在存储器区域的任何单个数据段中检测到较高数量的位错误的情况下，对存储器区域执行该更高数量的位错误的错误校正，同时检测存在更高级别的位错误。通过以这样的分级顺序执行更高级别的比特错误的纠错，可以在大多数数据访问中避免与这种纠错相关联的存储器等待时间，从而提高数据访问的性能。

2. 发明申请

US20120233498A1 HIERARCHICAL ERROR CORRECTION FOR LARGE MEMORIES 有权
标题翻译：大型记忆体的分层错误校正
公开(公告)号：US20120233498A1
公开(公告)日：2012-09-13
申请号：US13045307
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
发明人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
摘要翻译：提供了一种用于检测和校正存储在正在读取的存储器区域中的数据段中的第一数量的位错误的机制，同时检测该数据段中是否存在较高数量的位错误。在存储器区域的任何单个数据段中检测到较高数量的位错误的情况下，对存储器区域执行该更高数量的位错误的错误校正，同时检测存在更高级别的位错误。通过以这样的分级顺序执行更高级别的比特错误的纠错，可以在大多数数据访问中避免与这种纠错相关联的存储器等待时间，从而提高数据访问的性能。

3. 发明授权

US09542334B2 Memory management unit TAG memory with CAM evaluate signal 有权
标题翻译：具有CAM评估信号的存储器管理单元TAG存储器
公开(公告)号：US09542334B2
公开(公告)日：2017-01-10
申请号：US13213831
申请日：2011-08-19
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： G06F12/10 , G06F9/38
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) having compact bitcells with embedded partial A+B=K logic to generate two speculative hit/miss signals under control of a delayed evaluate signal. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。来自操作数（111,113）的PGZ编码的地址位（0:51）被带有进位值（Cout48）到具有嵌入的部分A + B = K的紧凑位单元的内容寻址存储器阵列（114）在延迟评估信号的控制下产生两个投机命中/未命中信号的逻辑。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

4. 发明授权

US09367475B2 System and method for cache access 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US09367475B2
公开(公告)日：2016-06-14
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/00 , G06F13/00 , G06F12/08 , G06F1/32
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

5. 发明授权

US09367437B2 Method and apparatus for reducing the number of speculative accesses to a memory array 有权
标题翻译：用于减少对存储器阵列的推测访问次数的方法和装置
公开(公告)号：US09367437B2
公开(公告)日：2016-06-14
申请号：US13831870
申请日：2013-03-15
申请人： Andrew C. Russell , Ravindraraj Ramaraju
发明人： Andrew C. Russell , Ravindraraj Ramaraju
IPC分类号： G06F12/00 , G06F12/02 , G06F9/34 , G06F12/06
CPC分类号： G06F12/00 , G06F9/34 , G06F12/0207 , G06F12/0215 , G06F12/06 , G06F2212/1028 , Y02D10/13
摘要： A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.
摘要翻译：一种方法包括：从基本操作数接收第一多个连续比特，其中来自基本操作数的第一多个连续比特的MSB是来自基本操作数的第二多个连续比特的LSB; 以及从偏移操作数接收第一多个连续比特，其中来自所述偏移操作数的所述第一多个连续比特的MSB是来自所述偏移操作数的第二多个连续比特的LSB。该方法包括将来自基本操作数的第一多个连续比特与来自该偏移操作数的第一多个连续比特相加以产生和值; 并且当和值的MSB的较低有效位等于零时，允许访问多个存储器阵列中的一个并且禁止对多个存储器阵列的其余部分的访问。

6. 发明授权

US09318158B2 Non-volatile memory using bi-directional resistive elements 有权
标题翻译：使用双向电阻元件的非易失性存储器
公开(公告)号：US09318158B2
公开(公告)日：2016-04-19
申请号：US14287463
申请日：2014-05-27
申请人： Frank K. Baker, Jr. , Perry H. Pelley , Ravindraraj Ramaraju
发明人： Frank K. Baker, Jr. , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C11/00 , G11C5/06 , G11C13/00
CPC分类号： G11C5/06 , G11C5/025 , G11C5/063 , G11C5/14 , G11C13/0004 , G11C13/0011 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.
摘要翻译：存储单元包括具有耦合到第一电源轨的阴极和耦合到内部节点的阳极的第一双向电阻元件，具有耦合到内部节点的阴极和耦合到内部节点的阳极的第二双向电阻元件第二电源轨，以及具有耦合到所述内部节点的控制电极的第一晶体管，耦合到第一位线的第一电流电极和耦合到第三电力轨的第二电流电极。

7. 发明授权

US09081693B2 Data type dependent memory scrubbing 有权
标题翻译：数据类型相关内存擦除
公开(公告)号：US09081693B2
公开(公告)日：2015-07-14
申请号：US13588243
申请日：2012-08-17
申请人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
发明人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
IPC分类号： G06F12/00 , G06F12/08 , G06F11/10
CPC分类号： G06F12/0895 , G06F11/106 , G06F11/1064 , Y02D10/13
摘要： A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.
摘要翻译：一种用于基于高速缓冲存储器的标签阵列的状态位的内容来控制存储器擦除速率的方法。更具体地说，高速缓冲存储器的标签阵列以比缓存的存储阵列的擦除速率更小的间隔进行擦除。对于保持标签数据完整性的重要性，这种提高的清洗率是值得赞赏的。基于指示被修改的标签阵列的状态位的内容，相应地擦除缓存存储阵列中的相应数据条目。如果修改的位被设置，则在处理标签条目之后擦除存储阵列中的条目。如果未设置修改的位，则以预定的擦洗间隔擦除存储阵列。

8. 发明申请

US20140269131A1 MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS 有权
标题翻译：具有省电功能的记忆用于不必要的阅读
公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

9. 发明授权

US08755244B2 Write contention-free, noise-tolerant multi-port bitcell 有权
标题翻译：写入无争用，耐噪声的多端口位单元
公开(公告)号：US08755244B2
公开(公告)日：2014-06-17
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C8/00 , G11C11/00
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

10. 发明授权

US08587356B2 Recoverable and reconfigurable pipeline structure for state-retention power gating 有权
标题翻译：用于状态保持功率门控的可恢复和可重新配置的管道结构
公开(公告)号：US08587356B2
公开(公告)日：2013-11-19
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

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