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1. 发明授权

US07678710B2 Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system 有权
标题翻译：使用低能量等离子体系制造高介电常数晶体管栅的方法和装置
公开(公告)号：US07678710B2
公开(公告)日：2010-03-16
申请号：US11614019
申请日：2006-12-20
申请人： Thai Cheng Chua , Steven Hung , Patricia M. Liu , Tatsuya Sato , Alex M. Paterson , Valentin Todorov , John P. Holland
发明人： Thai Cheng Chua , Steven Hung , Patricia M. Liu , Tatsuya Sato , Alex M. Paterson , Valentin Todorov , John P. Holland
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02175 , H01J37/32082 , H01J37/32146 , H01L21/02148 , H01L21/02266 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/316 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the invention also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform any desirable post treatment steps, and form the polysilicon and/or metal gate layers.
摘要翻译：本发明通常提供适于在衬底上形成高质量电介质栅极层的方法和装置。实施例考虑了一种方法，其中使用金属等离子体处理工艺代替标准氮化工艺以在衬底上形成高介电常数层。实施例进一步考虑了一种适于“植入”相对较低能量的金属离子的装置，以便减少对诸如二氧化硅层的栅极介电层的离子轰击损伤，并避免将金属原子并入到下面的硅中。通常，该方法包括以下步骤：形成高k电介质，然后终止沉积的高k材料的表面，以在栅电极和高k电介质材料之间形成良好的界面。本发明的实施例还提供一种簇工具，其适于形成高k电介质材料，终止高k电介质材料的表面，执行任何期望的后处理步骤，并形成多晶硅和/或金属栅极层。

2. 发明申请

US20070212896A1 METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM 有权
标题翻译：使用低能量等离子体系统制造高介电常数晶体闸门的方法和装置
公开(公告)号：US20070212896A1
公开(公告)日：2007-09-13
申请号：US11683984
申请日：2007-03-08
申请人： Christopher Olsen , Thai Chua , Steven Hung , Patricia Liu , Tatsuya Sato , Alex Paterson , Valentin Todorov , John Holland
发明人： Christopher Olsen , Thai Chua , Steven Hung , Patricia Liu , Tatsuya Sato , Alex Paterson , Valentin Todorov , John Holland
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02175 , H01J37/32082 , H01J37/32146 , H01L21/02148 , H01L21/02197 , H01L21/02266 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/316 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.
摘要翻译：本发明通常提供适于在衬底上形成高质量电介质栅极层的方法和装置。实施例考虑了一种方法，其中使用金属等离子体处理工艺代替标准氮化工艺以在衬底上形成高介电常数层。实施例进一步考虑了一种适于“植入”相对较低能量的金属离子的装置，以便减少对诸如二氧化硅层的栅极介电层的离子轰击损伤，并避免将金属原子并入到下面的硅中。通常，该方法包括以下步骤：形成高k电介质，然后终止沉积的高k材料的表面，以在栅电极和高k电介质材料之间形成良好的界面。

3. 发明授权

US06617794B2 Method for controlling etch uniformity 失效
公开(公告)号：US06617794B2
公开(公告)日：2003-09-09
申请号：US10016971
申请日：2001-12-14
申请人： Michael Barnes , John Holland , Valentin Todorov , Mohit Jain , Alexander Paterson
发明人： Michael Barnes , John Holland , Valentin Todorov , Mohit Jain , Alexander Paterson
IPC分类号： H01J724
CPC分类号： H01J37/32174 , H01J37/321
摘要： The present invention generally provides a method for processing a semiconductor substrate, wherein the method includes positioning a substrate in a processing chamber having at least a first and second coils positioned above the substrate and supplying a first electrical current to the first coil. The method further includes supplying a second current to the second coil and regulating a current ratio of electrical current supplied to the first and second coils with a power distribution network in communication with the first and second coils and a single power supply. The method may further include controlling plasma uniformity in a semiconductor processing chamber, wherein the control process includes positioning a first coil above the processing chamber, the first coil being concentrically positioned about a vertical axis of the processing chamber, and positioning a second coil above the processing chamber, the second coil being concentrically positioned about the vertical axis of the processing chamber and radially outward from the first coil. The control process may further include supplying electrical power to the first and second coils with a single power distribution network to selectively regulate a magnetic field intensity generated by the first and second coils above a workpiece in the processing chamber.

4. 发明授权

US06399507B1 Stable plasma process for etching of films 失效
标题翻译：用于蚀刻膜的稳定等离子体工艺
公开(公告)号：US06399507B1
公开(公告)日：2002-06-04
申请号：US09401603
申请日：1999-09-22
申请人： Padmapani Nallan , John Holland , Valentin Todorov , Thorsten Lill
发明人： Padmapani Nallan , John Holland , Valentin Todorov , Thorsten Lill
IPC分类号： H01L21302
CPC分类号： H01J37/321
摘要： In accordance with the present invention, process parameters are controlled to provide a stable etch plasma. We have discovered that it is possible to operate a stable plasma with a portion of the power deposited to the plasma being a capacitive contribution and a portion of the power deposited being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap
摘要翻译：根据本发明，控制工艺参数以提供稳定的蚀刻等离子体。我们已经发现，可以操作稳定的等离子体，其中一部分功率沉积到等离子体是电容性的，并且所沉积的功率的一部分是感应贡献。特别地，可以在两个工艺区域内获得稳定的等离子体。在第一区域中，电容性功率对施加到用于等离子体产生的电感耦合源的功率的梯度大于0.在第二区域中，等离子体稳定性受到控制，使得[∂Pcap/ ∠PRF]小于0，因此Pcap << PRF。通常，Pcap的幅度小于PRF大小的10％。此外，在具有双功率控制的等离子体处理装置中，在给予对等离子体发生源的功率施加时，通过增加蚀刻处理室中的压力来延长等离子体的稳定性。这使得能够使用较低功率应用进行等离子体生成的蚀刻工艺。将稳定的等离子体操作状态覆盖在其它工艺参数上以获得所需的蚀刻结果，以提供可靠的制造工艺。在稳定等离子体区域中的蚀刻工艺的操作使得能够使用定时蚀刻终点。例如，在蚀刻含硅层期间，可以使用蚀刻剂等离子体，其在蚀刻工艺的第一定时蚀刻部分期间相对于相邻层提供快速蚀刻和蚀刻选择性，以及在蚀刻过程中的不同蚀刻剂等离子体最终排放物监测到底层基板界面的蚀刻。此外，稳定的等离子体以基本上相同的速率帮助蚀刻掺杂和未掺杂的硅和多晶硅衬底，同时提供干净的蚀刻工艺。

5. 发明授权

US06706138B2 Adjustable dual frequency voltage dividing plasma reactor 有权
标题翻译：可调双频分压等离子体反应堆
公开(公告)号：US06706138B2
公开(公告)日：2004-03-16
申请号：US09931324
申请日：2001-08-16
申请人： Michael S. Barnes , John Holland , Alexander Paterson , Valentin Todorov , Farhad Moghadam
发明人： Michael S. Barnes , John Holland , Alexander Paterson , Valentin Todorov , Farhad Moghadam
IPC分类号： H01L21306
CPC分类号： H01J37/3244 , H01J37/32082
摘要： Apparatus and method for processing a substrate are provided. The apparatus for processing a substrate comprises: a chamber having a first electrode; a substrate support disposed in the chamber and providing a second electrode; a high frequency power source electrically connected to either the first or the second electrode; a low frequency power source electrically connected to either the first or the second electrode; and a variable impedance element connected to one or more of the electrodes. The variable impedance element may be tuned to control a self bias voltage division between the first electrode and the second electrode. Embodiments of the invention substantially reduce erosion of the electrodes, maintain process uniformity, improve precision of the etch process for forming high aspect ratio sub-quarter-micron interconnect features, and provide an increased etch rate which reduces time and costs of production of integrated circuits.
摘要翻译：提供了用于处理基板的设备和方法。用于处理衬底的设备包括：具有第一电极的腔室; 设置在所述室中并提供第二电极的衬底支撑件; 电连接到第一或第二电极的高频电源; 电连接到第一或第二电极的低频电源; 和连接到一个或多个电极的可变阻抗元件。可调谐可变阻抗元件以控制第一电极和第二电极之间的自偏压分压。本发明的实施例大大减少电极的侵蚀，保持工艺均匀性，提高用于形成高纵横比亚微米互连特征的蚀刻工艺的精度，并提供增加的蚀刻速率，从而减少集成电路的生产时间和成本。

6. 发明授权

US06660127B2 Apparatus for plasma etching at a constant etch rate 失效
标题翻译：用于以恒定蚀刻速率等离子体蚀刻的装置
公开(公告)号：US06660127B2
公开(公告)日：2003-12-09
申请号：US10075223
申请日：2002-02-12
申请人： Padmapani Nallan , John Holland , Valentin Todorov , Thorsten Lill
发明人： Padmapani Nallan , John Holland , Valentin Todorov , Thorsten Lill
IPC分类号： C23C1600
CPC分类号： H01J37/321
摘要： We have discovered a method which permits plasma etching at a constant etch rate. The constant etch rate is achieved by controlling plasma process parameters so that a stable plasma is obtained, with a portion of the power deposited to the plasma being a capacitive contribution, and a portion being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap
摘要翻译：我们已经发现了以恒定的蚀刻速率允许等离子体蚀刻的方法。通过控制等离子体工艺参数来实现恒定的蚀刻速率，从而获得稳定的等离子体，其中沉积到等离子体的功率的一部分是电容性贡献，并且部分是归纳贡献。特别地，可以在两个工艺区域内获得稳定的等离子体。在第一区域中，电容性功率对施加到用于等离子体产生的电感耦合源的功率的梯度大于0.在第二区域中，等离子体稳定性受到控制，使得[∂Pcap/ ∠PRF]小于0，因此Pcap << PRF。通常，Pcap的幅度小于PRF大小的10％。在稳定等离子体区域中的蚀刻工艺的操作使得能够使用定时蚀刻终点。

7. 发明授权

US5942889A Capacitive probe for in situ measurement of wafer DC bias voltage 失效
标题翻译：用于原位测量晶圆直流偏置电压的电容式探头
公开(公告)号：US5942889A
公开(公告)日：1999-08-24
申请号：US878855
申请日：1997-06-20
申请人： Peter K. Loewenhardt , Arthur Sato , Valentin Todorov
发明人： Peter K. Loewenhardt , Arthur Sato , Valentin Todorov
IPC分类号： G01R19/00 , G01R31/265 , H01J37/32 , H01L21/66
CPC分类号： B24B37/013 , G01R19/0061 , G01R31/265 , H01J37/32935 , H01L22/26
摘要： Apparatus and a concomitant method for estimating voltage on a wafer located in a process chamber. A probe, attached externally to a wall of the process chamber, detects voltage levels generated by a plasma within said process chamber. A relationship between the detected plasma voltage level and the wafer voltage is determined.
摘要翻译：用于估计位于处理室中的晶片上的电压的装置和伴随方法。在处理室的壁外部附接的探针检测由所述处理室内的等离子体产生的电压水平。确定检测到的等离子体电压电平和晶片电压之间的关系。

8. 发明授权

US06507155B1 Inductively coupled plasma source with controllable power deposition 失效
标题翻译：具有可控功率沉积的电感耦合等离子体源
公开(公告)号：US06507155B1
公开(公告)日：2003-01-14
申请号：US09544377
申请日：2000-04-06
申请人： Michael Barnes , John Holland , Valentin Todorov
发明人： Michael Barnes , John Holland , Valentin Todorov
IPC分类号： H01J724
CPC分类号： H01J37/32174 , H01J37/321
摘要： Method and apparatus for distributing power from a single power source to a plurality of coils disposed on a processing chamber which provides controllable plasma uniformity across a substrate disposed in the processing chamber. The apparatus for distributing power from a power source to two or more coils disposed on a process chamber comprises a connection between the power source and a first coil, a series capacitor connected between the power source and the second coil, and a shunt capacitor connected to a node between the second coil and the power source. The method for distributing power from one power source to a plurality of coils comprises connecting a first coil between the power source and a ground connection, connecting a first power distribution network to the power source, wherein each power distribution network comprises a series capacitor and a shunt capacitor, and connecting a second coil between the first power distribution network and a ground connection.
摘要翻译：用于将功率从单个电源分配到设置在处理室上的多个线圈的方法和装置，其在布置在处理室中的衬底上提供可控的等离子体均匀性。用于从电源将功率分配到设置在处理室上的两个或更多个线圈的装置包括电源和第一线圈之间的连接，连接在电源和第二线圈之间的串联电容器以及连接到第二线圈和电源之间的节点。用于从一个电源向多个线圈分配电力的方法包括将电源和接地连接之间的第一线圈连接，将第一配电网络连接到电源，其中每个配电网络包括串联电容器和并联电容器，并且在第一配电网络和接地连接之间连接第二线圈。

9. 发明授权

US06356097B1 Capacitive probe for in situ measurement of wafer DC bias voltage 有权
标题翻译：用于原位测量晶圆直流偏置电压的电容式探头
公开(公告)号：US06356097B1
公开(公告)日：2002-03-12
申请号：US09361649
申请日：1999-07-27
申请人： Peter K. Loewenhardt , Arthur Sato , Valentin Todorov
发明人： Peter K. Loewenhardt , Arthur Sato , Valentin Todorov
IPC分类号： G01R104
CPC分类号： G01R31/265 , B24B37/013 , G01R15/16 , G01R19/0061 , H01J37/32935 , H01L22/26
摘要： A method and apparatus for estimating voltage on a wafer located in a process chamber. A probe, embedded in a wall of the process chamber, detects voltage levels generated by a plasma within the process chamber. A relationship between the detected plasma voltage level and the wafer voltage is determined.
摘要翻译：一种用于估计位于处理室中的晶片上的电压的方法和装置。嵌入在处理室的壁中的探针检测由处理室内的等离子体产生的电压水平。确定检测到的等离子体电压电平和晶片电压之间的关系。

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