专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060062917A1 Vapor deposition of hafnium silicate materials with tris(dimethylamino)silane 审中-公开
标题翻译：硅酸铪材料与三（二甲基氨基）硅烷的蒸汽沉积
公开(公告)号：US20060062917A1
公开(公告)日：2006-03-23
申请号：US11223896
申请日：2005-09-09
申请人： Shankar Muthukrishnan , Tejal Goyani , Rahul Sharangpani , Shreyas Kher , Pravin Narwankar , Khaled Ahmed , Yi Ma
发明人： Shankar Muthukrishnan , Tejal Goyani , Rahul Sharangpani , Shreyas Kher , Pravin Narwankar , Khaled Ahmed , Yi Ma
IPC分类号： C23C16/00
CPC分类号： C23C16/308 , C23C16/401 , C23C16/56
摘要： In one embodiment, a method for forming a morphologically stable dielectric material is provided which includes exposing a substrate to a hafnium precursor, a silicon precursor and an oxidizing gas to form hafnium silicate material during a chemical vapor deposition (CVD) process and subsequently and optionally exposing the substrate to a post deposition anneal, a nitridation process and a thermal annealing process. In some examples, the hafnium and silicon precursors used during a metal-organic CVD (MOCVD) process are alkylamino compounds, such as tetrakis(diethylamino)hafnium (TDEAH) and tris(dimethylamino)silane (Tris-DMAS). In another embodiment, other metal precursors may be used to form a variety of metal silicates containing tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof.
摘要翻译：在一个实施方案中，提供了一种用于形成形态稳定的电介质材料的方法，其包括在化学气相沉积（CVD）工艺期间将衬底暴露于铪前体，硅前体和氧化气体以形成硅酸铪材料，随后和任选地将衬底暴露于后沉积退火，氮化工艺和热退火工艺。在一些实例中，在金属 - 有机CVD（MOCVD）方法中使用的铪和硅前体是烷基氨基化合物，例如四（二乙基氨基）铪（TDEAH）和三（二甲氨基）硅烷（Tris-DMAS）。在另一个实施方案中，其它金属前体可用于形成含有钽，钛，铝，锆，镧或其组合的各种金属硅酸盐。

2. 发明申请

US20060019033A1 Plasma treatment of hafnium-containing materials 审中-公开
标题翻译：含铪材料的等离子体处理
公开(公告)号：US20060019033A1
公开(公告)日：2006-01-26
申请号：US11167070
申请日：2005-06-24
申请人： Shankar Muthukrishnan , Rahul Sharangpani , Tejal Goyani , Pravin Narwankar , Shreyas Kher , Khaled Ahmed , Yi Ma
发明人： Shankar Muthukrishnan , Rahul Sharangpani , Tejal Goyani , Pravin Narwankar , Shreyas Kher , Khaled Ahmed , Yi Ma
IPC分类号： C23C16/00
CPC分类号： H01L21/0228 , C23C16/401 , C23C16/405 , C23C16/4488 , C23C16/45525 , C23C16/45529 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/0234 , H01L21/3141 , H01L21/3143 , H01L21/31637 , H01L21/31645
摘要： In one embodiment, a method for forming a dielectric material is provided which includes exposing a substrate sequentially to a metal-containing precursor and an oxidizing gas to form metal oxide (e.g., HfOx) during an ALD process and subsequently exposing the substrate to an inert plasma process and a thermal annealing process. Generally, the metal oxide contains hafnium, tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof. In one example, the inert plasma process contains argon and is free of nitrogen, while the thermal annealing process contains oxygen. In another example, an ALD process to form a metal oxide includes exposing the substrate sequentially to a metal precursor and an oxidizing gas containing water vapor formed by a catalytic water vapor generator. In an alternative embodiment, a method for forming a dielectric material is provide which includes exposing a substrate to a deposition process to form a metal oxide layer and subsequently exposing the substrate to a nitridation plasma process and a thermal annealing process to form metal oxynitride (e.g., HfOxNy).
摘要翻译：在一个实施例中，提供了一种用于形成介电材料的方法，其包括在ALD过程期间将衬底依次暴露于含金属的前体和氧化气体以形成金属氧化物（例如，HfO x x x）随后将衬底暴露于惰性等离子体工艺和热退火工艺中。通常，金属氧化物含有铪，钽，钛，铝，锆，镧或其组合。在一个实例中，惰性等离子体工艺包含氩并且不含氮，而热退火工艺含有氧。在另一个实例中，形成金属氧化物的ALD工艺包括将基板顺序地暴露于金属前体和含有由催化水蒸汽发生器形成的水蒸汽的氧化气体。在替代实施例中，提供了形成电介质材料的方法，其包括将衬底暴露于沉积工艺以形成金属氧化物层，并随后将衬底暴露于氮化等离子体工艺和热退火工艺以形成金属氮氧化物（例如，HfO x N N y）。

3. 发明申请

US20070049043A1 Nitrogen profile engineering in HI-K nitridation for device performance enhancement and reliability improvement 审中-公开
标题翻译：氮化硅工程在HI-K氮化中的设备性能提升和可靠性提高
公开(公告)号：US20070049043A1
公开(公告)日：2007-03-01
申请号：US11209472
申请日：2005-08-23
申请人： Shankar Muthukrishnan , Rahul Sharangpani , Tejal Goyani , Pravin Narwankar , Shreyas Kher , Yi Ma , Giuseppina Conti
发明人： Shankar Muthukrishnan , Rahul Sharangpani , Tejal Goyani , Pravin Narwankar , Shreyas Kher , Yi Ma , Giuseppina Conti
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , H01L21/02329 , H01L21/28202 , H01L21/3144 , H01L21/3145 , H01L21/31645 , H01L29/517
摘要： A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on the substrate. Finally, the substrate is exposed to a plasma comprising a nitrogen source while maintaining the voltage to form a nitrided gate dielectric on the substrate. In one embodiment, the voltage is induced on the substrate by applying a voltage to an electrostatic chuck supporting the substrate. In another embodiment, the voltage is induced on the substrate by applying a DC bias voltage to an electrode positioned adjacent the substrate.
摘要翻译：一种用于形成氮化栅极电介质的方法和装置。该方法包括使用等离子体氮化工艺将氮合并到电介质膜中以形成氮化栅极电介质。第一步涉及提供包括栅介质膜的衬底。第二步涉及在衬底上感应电压。最后，将衬底暴露于包含氮源的等离子体，同时保持电压以在衬底上形成氮化栅电介质。在一个实施例中，通过向支撑衬底的静电卡盘施加电压来在衬底上感应电压。在另一个实施例中，通过对邻近衬底定位的电极施加DC偏置电压来在衬底上感应出电压。

4. 发明申请

US20090242957A1 ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES 失效
标题翻译：用于非易失性存储器件的原子层沉积工艺
公开(公告)号：US20090242957A1
公开(公告)日：2009-10-01
申请号：US12059782
申请日：2008-03-31
申请人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
发明人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
IPC分类号： H01L21/28 , H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.
摘要翻译：本发明的实施例提供了用于形成存储器件的存储器件和方法。在一个实施例中，提供了一种存储器件，其包括设置在衬底的源极/漏极区域上的浮置栅极多晶硅层，设置在浮置栅极多晶硅层上的氧氮化硅层，设置在氧氮化硅层上的第一氧化铝层，设置在所述第一氧化铝层上的铪硅氮化物层，设置在所述铪硅氮氧化物层上的第二氧化铝层，以及设置在所述第二氧化铝层上的控制栅极多晶硅层。在另一个实施例中，提供了一种存储器件，其包括设置在布置在浮置多晶硅层上方的氧化硅层上的多晶硅介质叠层之间的控制栅极多晶硅层。多晶硅间介质堆叠包含由氮化硅层分隔的两个氮氧化硅层。

5. 发明授权

US07659158B2 Atomic layer deposition processes for non-volatile memory devices 失效
标题翻译：用于非易失性存储器件的原子层沉积工艺
公开(公告)号：US07659158B2
公开(公告)日：2010-02-09
申请号：US12059782
申请日：2008-03-31
申请人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
发明人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.
摘要翻译：本发明的实施例提供了用于形成存储器件的存储器件和方法。在一个实施例中，提供了一种存储器件，其包括设置在衬底的源极/漏极区域上的浮置栅极多晶硅层，设置在浮置栅极多晶硅层上的氧氮化硅层，设置在氧氮化硅层上的第一氧化铝层，设置在所述第一氧化铝层上的铪硅氮化物层，设置在所述铪硅氮氧化物层上的第二氧化铝层，以及设置在所述第二氧化铝层上的控制栅极多晶硅层。在另一个实施例中，提供了一种存储器件，其包括设置在布置在浮置多晶硅层上方的氧化硅层上的多晶硅介质叠层之间的控制栅极多晶硅层。多晶硅间介质堆叠包含由氮化硅层分隔的两个氮氧化硅层。

6. 发明授权

US08043907B2 Atomic layer deposition processes for non-volatile memory devices 失效
标题翻译：用于非易失性存储器件的原子层沉积工艺
公开(公告)号：US08043907B2
公开(公告)日：2011-10-25
申请号：US12687732
申请日：2010-01-14
申请人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
发明人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
IPC分类号： H01L21/8238
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.
摘要翻译：本发明的实施例提供了用于形成这种存储器件的存储器件和方法。在一个实施例中，提供了一种用于在衬底上制造非易失性存储器件的方法，其包括在衬底表面上沉积第一多晶硅层，在第一多晶硅层上沉积氧化硅层，在第一多晶硅层上沉积第一氧氮化硅层氧化硅层，在第一氧氮化硅层上沉积氮化硅层，在氮化硅层上沉积第二氮氧化硅层，以及在第二氮氧化硅层上沉积第二多晶硅层。在一些示例中，第一多晶硅层是浮置栅极，第二多晶硅层是控制栅极。

7. 发明申请

US20100102376A1 Atomic Layer Deposition Processes for Non-Volatile Memory Devices 失效
标题翻译：非易失性存储器件的原子层沉积工艺
公开(公告)号：US20100102376A1
公开(公告)日：2010-04-29
申请号：US12687732
申请日：2010-01-14
申请人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
发明人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.
摘要翻译：本发明的实施例提供了用于形成这种存储器件的存储器件和方法。在一个实施例中，提供了一种用于在衬底上制造非易失性存储器件的方法，其包括在衬底表面上沉积第一多晶硅层，在第一多晶硅层上沉积氧化硅层，在第一多晶硅层上沉积第一氧氮化硅层氧化硅层，在第一氧氮化硅层上沉积氮化硅层，在氮化硅层上沉积第二氮氧化硅层，以及在第二氮氧化硅层上沉积第二多晶硅层。在一些示例中，第一多晶硅层是浮置栅极，第二多晶硅层是控制栅极。

8. 发明授权

US07910446B2 Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices 有权
标题翻译：用于形成用于非易失性存储器件的多晶硅电介质的集成方案
公开(公告)号：US07910446B2
公开(公告)日：2011-03-22
申请号：US12163542
申请日：2008-06-27
申请人： Yi Ma , Shreyas Kher , Khaled Ahmed
发明人： Yi Ma , Shreyas Kher , Khaled Ahmed
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.
摘要翻译：提供了用于形成电子器件的电子器件和方法，其允许减小器件尺寸，同时还保持或减少用于非易失性存储器件的漏电流。在一个实施例中，提供了一种制造非易失性存储器件的方法。该方法包括在衬底上沉积浮栅多晶硅层，在浮栅多晶硅层上形成氧化硅层，在氧化硅层上沉积第一氮氧化硅层，在第一氮氧化硅上沉积高k电介质材料层在所述高k电介质材料上沉积第二氮氧化硅，以及在所述第二氮氧化硅层上形成控制栅极多晶硅层。在一个实施例中，高k电介质材料层包括铪硅氮氧化物。

9. 发明申请

US20050186765A1 Gate electrode dopant activation method for semiconductor manufacturing 有权
标题翻译：用于半导体制造的栅电极掺杂剂激活方法
公开(公告)号：US20050186765A1
公开(公告)日：2005-08-25
申请号：US10784904
申请日：2004-02-23
申请人： Yi Ma , Khaled Ahmed , Kevin Cunningham , Robert McIntosh , Abhilash Mayur , Haifan Liang , Mark Yam , Toi Leung , Christopher Olsen , Shulin Wang , Majeed Foad , Gary Miner
发明人： Yi Ma , Khaled Ahmed , Kevin Cunningham , Robert McIntosh , Abhilash Mayur , Haifan Liang , Mark Yam , Toi Leung , Christopher Olsen , Shulin Wang , Majeed Foad , Gary Miner
IPC分类号： H01L21/268 , H01L21/28 , H01L21/324 , H01L21/36 , C30B1/00 , H01L21/20 , H01L21/425 , H01L21/44
CPC分类号： H01L21/268 , H01L21/28035 , H01L21/324
摘要： In one embodiment, the invention generally provides a method for annealing a doped layer on a substrate including depositing a polycrystalline layer to a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer.
摘要翻译：在一个实施例中，本发明通常提供了一种用于退火衬底上的掺杂层的方法，包括将多晶层沉积到栅极氧化物层并用掺杂剂注入多晶层以形成掺杂的多晶层。该方法还包括将掺杂多晶层暴露于快速热退火以便容易地将掺杂剂分布在整个多晶层中。随后，该方法包括将掺杂多晶层暴露于激光退火以激活多晶层上部的掺杂剂。

10. 发明申请

US20060286763A1 GATE ELECTRODE DOPANT ACTIVATION METHOD FOR SEMICONDUCTOR MANUFACTURING 失效
标题翻译：用于半导体制造的门极电极激活方法
公开(公告)号：US20060286763A1
公开(公告)日：2006-12-21
申请号：US11428758
申请日：2006-07-05
申请人： Yi Ma , Khaled Ahmed , Kevin Cunningham , Robert McIntosh , Abhilash Mayur , Haifan Liang , Mark Yam , Toi Leung , Christopher Olsen , Shulin Wang , Majeed Foad , Gary Miner
发明人： Yi Ma , Khaled Ahmed , Kevin Cunningham , Robert McIntosh , Abhilash Mayur , Haifan Liang , Mark Yam , Toi Leung , Christopher Olsen , Shulin Wang , Majeed Foad , Gary Miner
IPC分类号： H01L21/76
CPC分类号： H01L21/268 , H01L21/28035 , H01L21/324
摘要： Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within a range from about 1×1019 atoms/cm3 to about 1×1021 atoms/cm3, wherein the doped polycrystalline layer contains silicon or may contain germanium, carbon, or boron. The substrate may be heated to a temperature of about 800° C. or higher, such as about 1,000° C., during the rapid thermal anneal. Subsequently, the doped polycrystalline layer may be exposed to a laser anneal and heated to a temperature of about 1,000° C. or greater, such within a range from about 1,050° C. to about 1,400° C., for about 500 milliseconds or less, such as about 100 milliseconds or less.
摘要翻译：本发明的实施方案通常提供了在衬底上形成掺杂的含硅材料的方法。在一个实施例中，该方法提供在电介质层上沉积多晶层并且用掺杂剂注入多晶层以形成掺杂浓度在约1×10 19原子/ cm 2范围内的掺杂多晶层其中掺杂的多晶层含有硅或可含锗，碳或硼。在快速热退火期间，衬底可以被加热到约800℃或更高，例如约1000℃的温度。随后，掺杂多晶层可以暴露于激光退火并加热至约1000℃或更高的温度，例如在约1050℃至约1400℃的温度下，持续约500毫秒或更短，例如约100毫秒或更少。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式